YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 772

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 15 Serial Communication Interface (SCI, IrDA)
Bit
5
4
Rev.7.00 Mar. 18, 2009 page 704 of 1136
REJ09B0109-0700
Bit Name
ORER
FER
Initial Value
0
0
R/W
R/(W) *
R/(W) *
Description
Overrun Error
Indicates that an overrun error occurred while
receiving and the reception has ended abnormally.
[Setting condition]
•
[Clearing condition]
•
Framing Error
Indicates that a framing error occurred while
receiving in asynchronous mode and the reception
has ended abnormally.
[Setting condition]
•
[Clearing condition]
•
When the next serial reception is completed
while RDRF = 1
The receive data prior to the overrun error is
retained in RDR, and the data received
subsequently is lost. Also, subsequent serial
reception cannot be continued while the ORER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued, either.
When 0 is written to ORER after reading ORER
= 1
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is
checked for a value of 0; the second stop bit is
not checked. If a framing error occurs, the
receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial
reception cannot be continued while the FER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued, either.
When 0 is written to FER after reading FER = 1
The FER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.