YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 262

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 6 Bus Controller (BSC)
6.6.5
Figure 6.21 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one T
output cycle) state, and the T
When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When
connecting DRAM provided with an EDO page mode, the OE signal should be connected to the
(OE ) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM
Rev.7.00 Mar. 18, 2009 page 194 of 1136
REJ09B0109-0700
Read
Write
Note: n = 2 to 5
Basic Timing
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0)
c1
and two T
T
p
Row address
c2
(column address output cycle) states.
High
High
p
T
(precharge cycle) state, one T
r
T
c1
Column address
T
c2
r
(row address