YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 235

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.10
REFCR specifies DRAM/synchronous DRAM interface refresh control.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Bit
15
14
13
12
Note:
Bit Name
CMF
CMIE
RCW1
RCW0
* Only 0 can be written, to clear the flag.
Refresh Control Register (REFCR)
Initial Value
0
0
0
0
R/W
R/(W) *
R/W
R/W
R/W
Description
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
•
•
[Setting condition]
When RTCOR = RTCNT
Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by the
CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is performed,
this bit is always cleared to 0 and cannot be
modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
CAS-RAS Wait Control
These bits select the number of wait cycles to be
inserted between the CAS assert cycle and RAS
assert cycle in a DRAM/synchronous DRAM
refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
When 0 is written to CMF after reading CMF = 1
while the RFSHE bit is cleared to 0
When CBR refreshing is executed while the
RFSHE bit is set to 1
Rev.7.00 Mar. 18, 2009 page 167 of 1136
Section 6 Bus Controller (BSC)
REJ09B0109-0700