YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 27

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4
5.5
5.6
5.7
Section 6 Bus Controller (BSC).........................................................................137
6.1
6.2
6.3
6.4
5.3.5
5.3.6
5.3.7
Interrupt Sources ................................................................................................................ 120
5.4.1
5.4.2
Interrupt Exception Handling Vector Table....................................................................... 121
Interrupt Control Modes and Interrupt Operation .............................................................. 127
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Usage Notes ....................................................................................................................... 134
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
Features .............................................................................................................................. 137
Input/Output Pins ............................................................................................................... 139
Register Descriptions ......................................................................................................... 142
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10 Refresh Control Register (REFCR) ...................................................................... 167
6.3.11 Refresh Timer Counter (RTCNT)......................................................................... 170
6.3.12 Refresh Time Constant Register (RTCOR) .......................................................... 170
Bus Control ........................................................................................................................ 171
6.4.1
IRQ Status Register (ISR)..................................................................................... 116
IRQ Pin Select Register (ITSR) ............................................................................ 117
Software Standby Release IRQ Enable Register (SSIER) .................................... 119
External Interrupts ................................................................................................ 120
Internal Interrupts.................................................................................................. 121
Interrupt Control Mode 0 ...................................................................................... 127
Interrupt Control Mode 2 ...................................................................................... 129
Interrupt Exception Handling Sequence ............................................................... 130
Interrupt Response Times ..................................................................................... 132
DTC and DMAC Activation by Interrupt ............................................................. 133
Conflict between Interrupt Generation and Disabling .......................................... 134
Instructions that Disable Interrupts ....................................................................... 135
Times when Interrupts Are Disabled .................................................................... 135
Interrupts during Execution of EEPMOV Instruction........................................... 135
Change of IRQ Pin Select Register (ITSR) Setting .............................................. 135
IRQ Status Register (ISR)..................................................................................... 136
Bus Width Control Register (ABWCR)................................................................ 143
Access State Control Register (ASTCR) .............................................................. 143
Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)............................................ 144
Read Strobe Timing Control Register (RDNCR) ................................................. 150
CS Assertion Period Control Registers H, L (CSACRH, CSACRL).................... 151
Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL)............................... 153
Bus Control Register (BCR) ................................................................................. 154
DRAM Control Register (DRAMCR) .................................................................. 156
DRAM Access Control Register (DRACCR) ....................................................... 164
Area Division ........................................................................................................ 171
Rev.7.00 Mar. 18, 2009 page xxv of lxvi
REJ09B0109-0700