YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 421

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.6
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12
shows the interrupt sources and their priority order.
Table 7.12 Interrupt Sources and Priority Order
Interrupt Name
DMTEND0A
DMTEND0B
DMTEND1A
DMTEND1B
Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for
the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt
controller independently. The priority of transfer end interrupts on each channel is decided by the
interrupt controller, as shown in table 7.12.
Figure 7.38 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is
always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0.
In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0
while the DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR
should be set so as to prevent the occurrence of a combination that constitutes a condition for
interrupt generation during setting.
Interrupt Sources
DTE/
DTME
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt
DTIE
Interrupt Source
Short Address Mode
Interrupt due to end of
transfer on channel 0A
Interrupt due to end of
transfer on channel 0B
Interrupt due to end of
transfer on channel 1A
Interrupt due to end of
transfer on channel 1B
Full Address Mode
Interrupt due to end of
transfer on channel 0
Interrupt due to break in
transfer on channel 0
Interrupt due to end of
transfer on channel 1
Interrupt due to break in
transfer on channel 1
Rev.7.00 Mar. 18, 2009 page 353 of 1136
Section 7 DMA Controller (DMAC)
Transfer end/transfer
break interrupt
Interrupt
Priority Order
High
Low
REJ09B0109-0700