YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 259

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.6
In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst
operation is also possible, using fast page mode.
6.6.1
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.4.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2
to 5), and continuous area (areas 2 to 5).
Table 6.4
Note:
With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait
states, etc.) for continuous DRAM space conform to the settings for area 2.
6.6.2
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
6.5 shows the relation between the settings of MXC2 to MXC0 and the shift size.
The MXC2 bit should be cleared to 0 when the DRAM interface is used.
RMTS2
0
1
* Reserved (setting prohibited) in the H8S/2378 Group.
DRAM Interface
Setting DRAM Space
Address Multiplexing
RMTS1
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space
0
1
0
1
RMTS0
1
0
1
0
1
0
1
Continuous
DRAM space
Normal space Normal space Normal space
Normal space Normal space
DRAM space
Area 5
Mode register settings of synchronous DRAM *
Continuous synchronous DRAM space *
Continuous
DRAM space
DRAM space
Reserved (setting prohibited)
Area 4
Rev.7.00 Mar. 18, 2009 page 191 of 1136
Section 6 Bus Controller (BSC)
Continuous
DRAM space
DRAM space
DRAM space
Area 3
REJ09B0109-0700
Continuous
DRAM space
DRAM space
DRAM space
DRAM space
Area 2