YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 313

KIT DEV EVAL H8S/2378 LCD

YLCDRSK2378

Manufacturer Part Number
YLCDRSK2378
Description
KIT DEV EVAL H8S/2378 LCD
Manufacturer
Renesas Electronics America
Series
H8®r
Datasheet

Specifications of YLCDRSK2378

Main Purpose
Displays, LCD Controller
Embedded
Yes, MCU, 16-Bit
Utilized Ic / Part
YLCDRSK2378
Primary Attributes
5.7" QVGA, Touch Screen
Secondary Attributes
Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
(2) Read Data Extension
If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is read-
accessed in DMAC/EXDMAC single address mode, the establishment time for the read data can
be extended by clock suspend mode. The number of states for insertion of the read data extension
cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in
DRAMCR when the read data will be extended. The extension of the read data is not in
accordance with the bits DDS and EDDS.
Figure 6.62 shows the timing chart when the read data is extended by two cycles.
Figure 6.62 Example of Timing when the Read Data Is Extended by Two States
(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2)
DACK or EDACK
Precharge-sel
DQMU, DQML
Address bus
SDRAMφ
Data bus
CKE
CAS
RAS
WE
φ
PALL ACTV
address
Column
T
p
address
address
Row
Row
T
r
READ
T
c1
Rev.7.00 Mar. 18, 2009 page 245 of 1136
T
cl
NOP
T
c2
Column address
Section 6 Bus Controller (BSC)
T
sp1
T
sp2
REJ09B0109-0700

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