JG82875 S L8DB Intel, JG82875 S L8DB Datasheet
JG82875 S L8DB
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... Intel 875P Chipset Datasheet ® Intel 82875P Memory Controller Hub (MCH) February 2004 Document Number: 252525-002 ...
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... C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corpora- tion. Intel, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other coun- tries. *Other names and brands may be claimed as the property of others. ...
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... I/O Mapped Registers ....................................................................................44 3.4.1 3.4.2 3.5 DRAM Controller/Host-Hub Interface Device Registers (Device 0) ...............46 ® Datasheet Intel 82875P MCH ...........................................................................................................13 ® 875P Chipset System Overview ..........................................................16 ® 82875P MCH Overview .......................................................................18 Host Interface....................................................................................18 System Memory Interface .................................................................18 Hub Interface ....................................................................................19 Communications Streaming Architecture (CSA) Interface ................19 AGP Interface ...
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... VID1—Vendor Identification Register (Device 1).............................. 79 DID1—Device Identification Register (Device 1) .............................. 79 PCICMD1—PCI Command Register (Device 1)............................... 80 PCISTS1—PCI Status Register (Device 1) ...................................... 81 RID1—Revision Identification Register (Device 1) ........................... 82 SUBC1—Sub-Class Code Register (Device 1) ................................ 82 ® Datasheet Intel 82875P MCH ...
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... Datasheet Intel 82875P MCH BCC1—Base Class Code Register (Device 1) .................................82 MLT1—Master Latency Timer Register (Device 1)...........................83 HDR1—Header Type Register (Device 1) ........................................83 (Device 1)..........................................................................................84 (Device 1)..........................................................................................89 (Device 1)..........................................................................................89 VID3—Vendor Identification Register (Device 3) ..............................93 DID3— ...
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... Mechanism for Detecting AGP 2.0 and AGP 3.0 ............ 136 AGP Target Operations .................................................................. 137 AGP Transaction Ordering ............................................................. 138 Support for PCI-66 Devices ............................................................ 138 8X AGP Protocol............................................................................. 138 5.3.7.1 Fast Writes ...................................................................... 139 5.3.7.2 PCI Semantic Transactions on AGP ............................... 139 ® Datasheet Intel 82875P MCH ...
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... MCH Ballout.................................................................................................151 7.2 Package Information ....................................................................................162 8 Testability 8.1 XOR Test Mode Initialization .......................................................................165 8.1.1 ® Datasheet Intel 82875P MCH 5.4.0.1 Supported ACPI States ...................................................139 External Thermal Sensor Interface Overview .................................140 5.5.1.1 External Thermal Sensor Usage Model...........................141 ..............................................................................143 ...............................................................151 .............................................................................................................165 XOR Chain Definition ...
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... Figures 1 Intel 2 Intel 3 Intel 4 Full and Warm Reset Waveforms .................................................................. 37 5 Conceptual Intel 6 Configuration Mechanism Type 0 Configuration Address to PCI Address Mapping........................................................................................... 43 7 Configuration Mechanism Type 1 Configuration Address to PCI Address Mapping........................................................................................... 44 8 PAM Register Attributes ................................................................................ 60 9 Memory System Address Map..................................................................... 118 10 Detailed Memory System Address Map ...................................................... 118 11 Single-Channel Mode Operation ...
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... XOR Chain 8 (40 Inputs) Output Pins: TESTP8, TESTP8...........................172 45 XOR Chain 9 (62 Inputs) Output Pins: RSB2, DEFER# ..............................173 46 XOR Chain 10 (9 Inputs) Output Pins: RS0#, RS1#....................................173 47 XOR Chain 11 (9 Inputs) Output Pins: BREQ0#, CPURST#.......................174 48 XOR Excluded Pins .....................................................................................174 ® Datasheet Intel 82875P MCH 9 ...
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... Revision History Revision -001 • Initial Release • Added Note 12 to the VCC Core Voltage of Table 32, “DC Operating Characteristics“ -002 • Updated Note 6 of Table 33, “DC Characteristics“. 10 Description ® Intel 82875P MCH Date April 2003 February 2004 Datasheet ...
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... Intel 82875P MCH Features Host Interface Support I ® — Intel Pentium 4 processor 0.13 micron process / ® Intel Pentium 4 processor process — VTT 1.1 V – 1.55 V ranges — 64-bit FSB frequencies of 400 MHz (100 MHz bus clock), 533 MHz (133 MHz bus clock), and 800 MHz (200 MHz bus clock). Maximum theoretical BW of 6.4 GB/s. — ...
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... This page is intentionally left blank. Intel ® Datasheet 82875P MCH ...
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... Hyper-Threading Technology requires a computer system with an Intel Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See <<http://www.intel.com/info/hyperthreading/>> for more information including details on which processors support HT Technology. ® Intel 82875P MCH Datasheet ® ...
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... Fifth generation I/O Controller Hub component that contains additional functionality ® Intel ICH5 compared to the Intel The physical PCI bus that is driven directly by the ICH5 component. Communication Primary PCI between PCI and the MCH occurs over HI. Note that even though the Primary PCI bus is referred to as PCI it is not PCI Bus 0 from a configuration standpoint ...
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... JEDEC Double Data Rate (DDR) SDRAM Specification ® Intel PC SDRAM Specification Accelerated Graphics Port Interface Specification, Revision 3.0 Digital Visual Interface (DVI) Specification, Revision 1.0 NOTE: For additional related documents, refer to the Intel ® Intel 82875P MCH Datasheet Description ® ® ...
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... The 82801ER ICH5R elevates Serial ATA storage performance to the next level with Intel The ACPI compliant ICH5 platform can support the Full-on, Stop Grant, Suspend to RAM, Suspend to Disk, and Soft-Off power management states ...
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... Figure 1. Intel 875P Chipset System Block Diagram AGP 8x/4x CSA Interface Gigabit Ethernet USB 2.0 8 ports, 480 Mb/s GPIO 2 Serial ATA Ports 150 MB/s 2 ATA 100 Ports AC '97 3 CODEC support ® Intel 82875P MCH Datasheet Processor 400/533/800 MHz System Bus Intel ® ...
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... Registered DIMMs not supported • Supports opportunistic refresh • SPD (Serial Presence Detect) scheme for DIMM detection support • Suspend-to-RAM support using CKE • Supports configurations defined in the JEDEC DDR1 DIMM specification only • Performance Acceleration Technology support 18 ® Intel 82875P MCH Datasheet ...
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... The MCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. The MCH contains a 32-deep AGP request queue. High-priority accesses are supported. ® Intel 82875P MCH Datasheet Introduction 19 ...
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... MT/s DDR-DRAM 1/1 266 MT/s DDR-DRAM 3/2 266 MT/s DDR-DRAM 4/5 333 MT/s DDR-DRAM 5/4 320 MT/s DDR-DRAM 1/1 400 MT/s DDR-DRAM Intel Peak Bandwidth 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.7 GB/s 2.6 GB/s 3.2 GB/s ® 82875P MCH Datasheet ...
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... MCH host bridge. All processor control signals follow normal convention indicates an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix. ® Intel 82875P MCH Datasheet Input pin Output pin Bi-directional Input/Output pin Sustained Tri-state ...
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... Signal Description ® Figure 2. Intel 82875P MCH Interface Block Diagram HA[31:3]# HD[63:0]# HREQ[4:0]# CPURST# DINV[3:0]# HADSTB[1:0]# HDSTBP[3:0]#, HDSTBN[3:0]# BSEL[1:0] PROCHOT# SCS_A[3:0]# SMAA_A[12:0] SBA_A[1:0] SRAS_A# SCAS_A# SDQ_A[63:0] SECC_A[7:0] SDQS_A[8:0] SCKE_A[3:0] SCMDCLK_A[5:0], SCMDCLK_A[5:0]# SCS_B[3:0]# SMAA_B[12:0] SBA_B[1:0] SRAS_B# SCAS_B# SDQ_B[63:0] SECC_B[7:0] SDQS_B[8:0] SCKE_B[3:0] SCMDCLK_B[5:0], SCMDCLK_B[5:0]# ...
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... DINV[x]# Data Bits DINV3# HD[63:48]# 4X DINV2# HD[47:32]# DINV1# HD[31:16]# DINV0# HD[15:0]# NOTE: This signal is called DBI[3:0] in the Intel processor specification. Data Ready: This signal is asserted for each cycle that data is transferred. Signal Description Description ® ICH5) is asserted and for 23 ...
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... In the second half the signals carry additional information to define the complete 2X transaction type. The transactions supported by the MCH Host bridge are defined in Description Data Bits HD[63:48]#, DINV3# HD[47:32]#, DINV2# HD[31:16]#, DINV1# HD[15:0]#, DINV0# Chapter ® Intel 82875P MCH Datasheet 5. ...
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... DP[3:0]# HA[35:32] RSP# IERR# BINIT# MCERR# ® Intel 82875P MCH Datasheet O Host Target Ready: This signal indicates that the target of the processor transaction is able to enter the data transfer phase. I/0 Processor Hot: This signal informs the chipset when processor Tj>thermal monitor trip point. ...
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... There is one SCKE_A per DRAM row, toggled on the positive edge of SCMDCLK_A. I/O ECC Data bits: These signals provide the 8-bit ECC data, running at 2X data rate. The data is source synchronous using the DQS Strobes. SSTL-2 Description ® Intel 82875P MCH Datasheet ...
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... SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] SDQS_B[8:0] SCKE_B[3:0] SECC_B{7:0] ® Intel 82875P MCH Datasheet Type Differential DDR Clock: SCMDCLK_Bx and SCMDCLK_Bx# pairs are differential clock outputs. The crossing of the positive edge of O SCMDCLK_Bx and the negative edge of SCMDCLK_Bx# is used to SSTL_2 sample the address and control signals on the DRAM. There are three pairs to each DIMM ...
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... Packet Data: CI[10:0] are the data signals used for CI read and write operations. Packet Strobe: CISTRS is one of two differential strobe signals used to transmit or receive packet data over CI. Packet Strobe Complement: CISTRF is one of two differential strobe signals used to transmit or receive packet data over CI. ® Intel 82875P MCH Datasheet ...
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... The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 3. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing). ® Intel 82875P MCH Datasheet Type Pipelined Read: This signal is asserted by the current master to indicate a full width address queued by the target ...
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... Reserved in AGP 3.0 signaling mode 100 Reserved 101 Reserved 110 Reserved 111 The master has been given permission to start a bus transaction. The master may queue AGP requests by asserting GPIPE# (4X signaling mode) or start a PCI transaction by asserting GFRAME(#). Description Description ® Intel 82875P MCH Datasheet ...
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... The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 2. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing). ® Intel 82875P MCH Datasheet Type AD Bus Strobe-0: GADSTB0 provides timing for 4X clocked data on GAD[15:0] and GC/BE[1:0]# in AGP 2 ...
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... GAD[31:0] signals at any given time. Parity: This signal is not used on AGP transactions but is used during I/O GFRAME(#) based transactions as defined by the PCI specification. GPAR is AGP not used during fast writes. This signal contains an internal pull-up. Description ® Intel 82875P MCH Datasheet ...
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... LVTTL (3.3 V) EXTTS# LVTTL (3.3 V) ® Intel 82875P MCH Datasheet Type Dynamic Bus Inversion LO: This signal goes along with GAD[15:0] to indicate whether GAD[15:0] must be inverted on the receiving end. • DBI_LO= 0: GAD[15:0] are not inverted so receiver may use as is. • DBI_LO= 1: GAD[15:0] are inverted so receiver must invert before use. ...
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... GVSWING GRCOMP HI_VREF HI_RCOMP HI_SWING CI_VREF CI_RCOMP CI_SWING NOTE: Reference the Intel 34 Type Host Data Reference Voltage: HDVREF[1:0] are reference voltage inputs for I the data signals of the host AGTL+ interface. I/O Host RCOMP: HDRCOMP is used to calibrate the host AGTL+ I/O buffers. ...
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... V Supply: This supply is used for XOR Chain testing. VCC_DDR VCC for System Memory: VCC_DDR is 2.6 V for DDR. Analog VCC for System Memory: This signal is a 1.5 V supply for DDR. The supply VCCA_DDR requires special filtering. Refer to the Intel 2.9 MCH Sequencing Requirements Power Plane and Sequencing Requirements: • ...
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... Voltage OR TESTIN# High AGP 3.0: Strap Sampled Low Voltage OR TESTIN# High All Z Normal Normal Description Description AGP 2.0: Strap Sampled Low Voltage AND TESTIN# Low AGP 3.0: Strap Sampled High Voltage AND TESTIN# Low All Z XOR Mode ® Intel 82875P MCH Datasheet ...
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... RSTIN#) is asserted and PWROK is deasserted (see PCIRST# (MCH RSTIN#) is asserted and PWROK is also asserted. Table 3. Full and Warm Reset States Reset State Full Reset Warm Reset Does Not Occur Normal Operation ® Intel 82875P MCH Datasheet 1 ms Min 1 ms Unknown Full Reset Warm Reset Table RSTIN# ...
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... Signal Description 38 This page is intentionally left blank. ® Intel 82875P MCH Datasheet ...
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... That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note that software does not need to perform a read-merge-write operation for the Configuration Address (CONFIG_ADDRESS) register. ® Intel 82875P MCH Datasheet Register Description Description 3 ...
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... Registers returned. (“Reserved” registers can bits in size). Writes to “Reserved” registers have no effect on the MCH. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure. Reads to “Intel Reserved” registers may return a non-zero value. ...
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... PCI 0 while the secondary side is the standard PCI expansion bus. Note: A physical PCI bus 0 does not exist and that HI and the internal devices in the MCH and ICH5 logically constitute PCI Bus 0 to configuration software. Figure 5. Conceptual Intel 3.3 Routing Configuration Accesses The MCH supports two bus interfaces: HI and AGP/PCI ...
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... If the cycle is forwarded to the ICH5 via HI, the ICH5 compares the non-zero Bus Number with the Secondary Bus Number and Subordinate Bus Number Registers of its PCI-to-PCI bridges to determine if the configuration cycle is meant for Primary PCI, one of the ICH5’s HIs downstream PCI bus. 42 Figure 7. This HI configuration cycle will be ® Intel 82875P MCH Datasheet ...
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... Register, and less than or equal to the value programmed into the Subordinate Bus Number Register the configuration cycle is targeting a PCI bus downstream of the targeted interface. The MCH will generate a Type 1 PCI configuration cycle on PCI_B/AGP. The address bits will be mapped as described in ® Intel 82875P MCH Datasheet CONFIG_ADDRESS ...
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... Number, and Register Number for which a subsequent configuration access is intended Reserve Bus Device 1 d Number Number Bus Device 0 Number Number 0CF8h Accessed as a DWord 00000000h R/W 32 bits Reg. Index X X Function Number Reg. Index 0 1 Function Number ® Intel 82875P MCH Datasheet ...
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... CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Bit Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, any I/O access to the 31:0 CONFIG_DATA register will be mapped to configuration space using the contents of CONFIG_ADDRESS. ® Intel 82875P MCH Datasheet Descriptions 0CFCh 00000000h R/W 32 bits Descriptions ...
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... Subsystem Vendor Identification Subsystem Identification Intel Reserved Capabilities Pointer Intel Reserved AGP Miscellaneous Configuration Graphics Control CSA Basic Control Intel Reserved DRAM Error Data Register DRAM Error Syndrome DRAM Error Status Intel Reserved FPLL Clock Control Intel Reserved Programmable Attribute Map 0 ...
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... AGP MTT Control Register AGP Low Priority Transaction Timer Intel Reserved Top of Used DRAM MCH Configuration Error Status Error Command SMI Command SCI Command Intel Reserved Scratchpad Data Intel Reserved Capability Identification Intel Reserved Register Description Default Value Access 00h RO, R/W ...
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... The VID Register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register, uniquely identify any PCI device. Bit Vendor Identification (VID)—RO. This register field contains the PCI standard identification for 15:0 Intel, 8086h. 3.5.2 DID—Device Identification Register (Device 0) Address Offset: Default Value: ...
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... SERR Enable (SERRE)—R/W. This bit is a global enable bit for Device 0 SERR messaging. The MCH does not have an SERR signal. The MCH communicates the SERR condition by sending an SERR message over HI to the Intel 1 = MCH is enabled to generate SERR messages over HI for specific Device 0 error conditions that are individually enabled in the ERRCMD register ...
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... A list of new capabilities is accessed via 4 register CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the AGP capability standard register resides. 3:0 Reserved 50 06–07h 0090h RO, R/WC 16 bits Descriptions ® Intel 82875P MCH Datasheet ...
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... This register contains the Base Class Code of the MCH Device 0. Bit Base Class Code (BASEC)—RO. This is an 8-bit value that indicates the Base Class Code for the MCH Device 0. 7:0 06h = Bridge device. ® Intel 82875P MCH Datasheet 08h See following table RO 8 bits Descriptions ...
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... This register identifies the header layout of the configuration space. No physical register exists at this location. Bit PCI Header (HDR)—RO. This field always returns 0 to indicate that the MCH is a single-function 7:0 device with standard header layout. 52 0Dh 00h RO 8 bits Descriptions 0Eh 00h RO 8 bits Descriptions ® Intel 82875P MCH Datasheet ...
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... PCI specification for base address registers. Memory Space Indicator (MSPACE)—RO. Hardwired identify the aperture range memory range as per the specification for PCI base address registers. ® Intel 82875P MCH Datasheet 10 13h – 00000008h ...
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... Capabilities Pointer Address—RO. This field contains the pointer to the offset of the first 7:0 capability ID register block. In this case the first capability is the Product-Specific Capability, which is located at offset E4h. 54 2C–2Dh 0000h R/WO 16 bits Descriptions 2E–2Fh 0000h R/WO 16 bits Descriptions 34h E4h RO 8 bits Descriptions ® Intel 82875P MCH Datasheet ...
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... Enable. 0 Reserved 3.5.15 GC—Graphics Control Register (Device 0) Address Offset: Default Value: Access: Size: Bit 7:2 Reserved. Default = 0 3 Reserved. Default =1 1:0 Reserved. Default = 0 ® Intel 82875P MCH Datasheet 51h 00h R/W 8 bits Descriptions 52h 0000_1000h R/W, R/W/L 8 bits Descriptions Register Description 55 ...
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... Once the error flag bits are set as a result of an error, this bit field is locked and does not change as a result of a new error. 11:0 Reserved (RO. 56 53h 0000_000sb (s=Strap value) R/ bits Description 58 5Bh – Undefined RO 32 bits No Description ® Intel 82875P MCH Datasheet ...
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... Access: Size: Sticky: This register will have an undefined value when no ECC errors have been logged. Bit 7:1 Reserved Error Channel—RO Error Detected on Channel Error Detected on Channel B. ® Intel 82875P MCH Datasheet 5Ch Undefined RO 8 bits No Description 5Dh Undefined RO 8 bits ...
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... Writing a 1 cleanly disables the memory and memory I/O clocks of the chipset core and DDR interface from the DLL outputs. 3:2 Intel Reserved (Default=00) FSB PLL Sync (FPLLSYNC)—R/ After writing a 1, writing a 0 causes the FSB PLL to synchronize the memory to the processor 1 clock ...
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... Reserved the time that AGP access to the PAM region occurs, the targeted PAM segment must be programmed to be both readable and writable. ® Intel 82875P MCH Datasheet 90 96h (PAM0–PAM6) – 00h R/ bits Bits [5, 1] Bits [ Disabled DRAM is disabled and all accesses are directed to ...
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... ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension ® Intel 82875P MCH Datasheet 90h 90h 90h 91h 91h 92h 92h 93h 93h 94h ...
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... Bit Hole Enable (HEN)—R/W. This field enables a memory hole in DRAM space. The DRAM that lies “behind” this space is not remapped Disable. No memory hole Enable. Memory hole from MB. 6:0 Reserved ® Intel 82875P MCH Datasheet Table Table 7. Table 7. 97h 00h ...
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... SMM space. SMM DRAM is not remapped simply made visible if the conditions are right to 2:0 access SMM space, otherwise the access is forwarded to HI. Since the MCH supports only the SMM space between A0000h and BFFFFh, this field is hardwired to 010. 62 9Dh 02h R/W, RO, Lock 8 bits Descriptions ® Intel 82875P MCH Datasheet ...
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... TSEG Enable (T_EN)— R/W/L. This bit is for enabling of SMRAM memory for Extended SMRAM 0 space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Note that once D_LCK is set, this bit becomes read only. ® Intel 82875P MCH Datasheet 9Eh 38h R/W, R/WC, RO, Lock ...
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... Greater Than Four Gigabyte Support (GT4GIG)—RO. Hardwired to 0 indicating that the MCH 5 does not support addresses greater than 4 GB. 64 A0h–A3h 00300002h RO 32 bits Descriptions A4–A7h 1F000217h in AGP 2.0; 1F004A13h in AGP 3.0 mode RO 32 bits Descriptions ® Intel 82875P MCH Datasheet ...
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... MCH 2X is not supported. 3.5.27 AGPCMD—AGP Command Register (Device 0) Address Offset: Default Value: Access: Size: This register provides control of the AGP operational parameters. ® Intel 82875P MCH Datasheet Descriptions A8–ABh 00000000h in AGP 2.0 mode 00000A00h in AGP 3.0 mode RO, R/W 32 bits Register Description ...
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... AGP 2.0 signaling) 010= 2X transfer mode (NOT SUPPORTED) 2:0 100= 4X transfer mode (for AGP 2.0 signaling) AGP 3.0 001= 4X transfer mode (for AGP 3.0 signaling) 010= 8X transfer mode (for AGP 3.0 signaling) 100= Reserved 66 Descriptions ® Intel 82875P MCH Datasheet ...
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... Override (OVER4X)—R/W. This back-door register bit allows the BIOS to force 1X mode for AGP 2.0 and 4X mode for AGP 3.0. Note that this bit must be set by the BIOS before AGP configuration override 1 = The RATE[2:0] bit in the AGPSTS register will be read as a 001. ® Intel 82875P MCH Datasheet B0–B3h 00000000h RO, R/W 32 bits Descriptions ...
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... Note that it should be modified only when the GTLB has been disabled. 11:0 Reserved 68 B4h 00h RO, R/W 8 bits Descriptions B8–BBh 00000000h RO, R/W 32 bits Descriptions ® Intel 82875P MCH Datasheet ...
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... AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to another agent. 2:0 Reserved ® Intel 82875P MCH Datasheet BCh 10h RO, R/W 8 bits Descriptions ...
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... NOTE: Even if the OS does not need any PCI space, TOUD should never be programmed above FEC0_0000h. If TOUD is programmed above this, address ranges that are reserved will become accessible to applications. 2:0 Reserved 70 BDh 10h RO, R/W 8 bits Descriptions C4–C5h 0400h RO, R/W 16 bits Descriptions ® Intel 82875P MCH Datasheet ...
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... FSBFREQ[1:0] =01 FSBFREQ[1:0] =10 FSBFREQ[1:0] =10 11:10 All other combinations are Intel Reserved Note that Memory I/O Clock always runs at 2X the frequency of the memory clock NOTE: When writing a new value to this register, software must perform a clock synchronization 9:6 Reserved MDA Present (MDAP)—R/W. This bit works with the VGA Enable bits in the BCTRL1 register of Device 1 to control the routing of processor-initiated transactions targeting MDA compatible I/O and memory address ranges ...
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... BSEL[1:0] pins and is latched at the rising edge of PWROK Core Frequency is 100 MHz and the FSB frequency is 400 MHz 1 Core Frequency is 133 MHz and the FSB frequency is 533 MHz 10 = Core Frequency is 200 MHz and the FSB frequency is 800 MHz 11 = Reserved 72 Descriptions ® Intel 82875P MCH Datasheet ...
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... ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated. Note: Software must write clear bits that are set. Bit 15:10 Intel Reserved Non-DRAM Lock Error (NDLOCK)—R/WC Lock operation detected MCH has detected a lock operation to memory space that did not map into DRAM. This bit is cleared when software writes it. Software Generated SMI Flag— ...
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... EAP fields with the multiple bit error signature and the MEF bit will also be set. Software must write clear this bit and unlock the error logging mechanism. 74 Descriptions ® Intel 82875P MCH Datasheet ...
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... ERRSTS register. The actual generation of the SERR message is globally enabled for Device 0 via the PCI Command register. Bit 15:10 Intel Reserved SERR on Non-DRAM Lock (LCKERR)—R/ Disable Enable. The MCH will generate a HI SERR special cycle when a processor lock cycle is detected that does not hit system memory. SERR Multiple-Bit DRAM ECC Error (DMERR)— ...
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... Enable. The MCH generates an SCI HI special cycle when the DRAM controller detects a single bit error. For systems that do not support ECC, this bit must be disabled. 6:0 Reserved 76 CC–CDh 0000h RO, R/W 16 bits Descriptions CE–CFh 0000h RO, R/W 16 bits Descriptions ® Intel 82875P MCH Datasheet ...
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... Capability Identifier register (ACAPID). If AGP is disabled, this field has the value 00h signifying the end of the capabilities linked list. CAP_ID—RO. This field has the value 09h to identify the CAP_ID assigned by the PCI SIG for 7:0 Vendor Dependent CAP_PTR. ® Intel 82875P MCH Datasheet DE–DFh 0000h R/W 16 bits Descriptions E4h– ...
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... RO R/W 01h RO — — 00h RO 00h R/W 00h R/W 00h RO R/W F0h RO R/W 00h RO R/W 02A0h RO R/WC FFF0h RO R/W 0000h RO R/W FFF0h RO R/W 0000h RO R/W — — 00h RO R/W — — 00h RO R/W — — ® Intel 82875P MCH Datasheet ...
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... The VID Register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register, uniquely identify any PCI device. Bit Vendor Identification Device 1 (VID1)—RO. This register field contains the PCI standard 15:0 identification for Intel, 8086h. 3.6.2 DID1—Device Identification Register (Device 1) Address Offset: Default Value: ...
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... MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers. IO Access Enable (IOAE)—R/ Disable. All of Device 1’s I/O space is disabled Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and IOLIMIT1 registers. 80 04–05h 0000h RO, R/W 16 bits Descriptions ® Intel 82875P MCH Datasheet ...
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... Fast Back-to-Back (FB2B)—RO. Hardwired to 1. The AGP/PCI_B interface always supports fast 7 back to back writes. 6 Reserved 5 66/60 MHz Capability (CAP66)—RO. Hardwired to 1. The AGP/PCI bus is 66 MHz capable. 4:0 Reserved ® Intel 82875P MCH Datasheet 06–07h 00A0h RO, R/WC 16 bits Descriptions Register Description 81 ...
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... Base Class Code (BASEC)—RO. This is an 8-bit value that indicates the Base Class Code for the MCH Device 1. 7:0 06h = Bridge device. 82 08h See following table RO 8 bits Descriptions 0Ah 04h RO 8 bits Descriptions 0Bh 06h RO 8 bits Descriptions ® Intel 82875P MCH Datasheet ...
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... Primary Bus Number (PBUSN—RO. Configuration software typically programs this field with the 7:0 number of the bus on the primary side of the bridge. Since Device internal device and its primary bus is always 0, these bits are read only and are hardwired to 0. ® Intel 82875P MCH Datasheet 0Dh 00h RO, R/W ...
Page 84
... This register controls the bus tenure of the MCH on AGP/PCI the same way Device 0 MLT controls the access to the PCI_A bus. Bit 7:3 Secondary MLT Counter Value (MLT)—R/W. Programmable, default = 0 (SMLT disabled) 2:0 Reserved 84 19h 00h R/W 8 bits Descriptions 1Ah 00h R/W 8 bits Descriptions 1Bh 00h RO, R/W 8 bits Descriptions ® Intel 82875P MCH Datasheet ...
Page 85
... Bit I/O Address Limit (IOLIMIT)—R/W. This field corresponds to A[15:12] of the I/O address limit of 7:4 Device 1. Devices between this upper limit and IOBASE1 will be passed to AGP/PCI_B. 3:0 Reserved ® Intel 82875P MCH Datasheet 1Ch F0h RO, R/W 8 bits Descriptions 1Dh ...
Page 86
... Fast Back-to-Back (FB2B)—RO. Hardwired to 1. The MCH target, supports fast back-to- 7 back transactions on PCI_B/AGP. 6 Reserved 66/60 MHz capability (CAP66)—RO. Hardwired to 1. The AGP/PCI_B bus is capable of 66 MHz 5 operation. 4:0 Reserved 86 1E–1Fh 02A0h RO, R/WC 16 bits Descriptions ® Intel 82875P MCH Datasheet ...
Page 87
... Bit Memory Address Base (MBASE)—R/W. This field corresponds to A[31:20] of the lower limit of 15:4 the memory range that will be passed by the Device 1 bridge to AGP/PCI_B. 3:0 Reserved ® Intel 82875P MCH Datasheet 20–21h FFF0h RO, R/W 16 bits Descriptions Register Description ...
Page 88
... Memory Address Limit (MLIMIT)—R/W. This field corresponds to A[31:20] of the memory 15:4 address that corresponds to the upper limit of the range of memory accesses that will be passed by the Device 1 bridge to AGP/PCI_B. 3:0 Reserved 88 22–23h 0000h RO, R/W 16 bits Descriptions ® Intel 82875P MCH Datasheet ...
Page 89
... Bit Prefetchable Memory Address Limit (PMLIMIT)—R/W. This field corresponds to A[31:20] of the 15:4 upper limit of the address range passed by bridge Device 1 across AGP/PCI_B. 3:0 Reserved ® Intel 82875P MCH Datasheet 24–25h FFF0h RO, R/W 16 bits Descriptions 26–27h ...
Page 90
... All references to MDA and VGA space are routed to HI. Illegal combination. All VGA references are routed to this bus. MDA references are routed to HI. All VGA references are routed to this bus. MDA references are routed to HI. Table 9. Table 9. ® Intel 82875P MCH Datasheet ...
Page 91
... The MCH does not assert an SERR message upon receipt of a target abort on PCI_B. SERR 0 messaging for Device 1 is globally enabled in the PCICMD1 register The MCH generates an SERR message over HI upon receiving a target abort on PCI_B. ® Intel 82875P MCH Datasheet 40h 00h RO, R/W ...
Page 92
... R/W 00h R/W 00h R/W 00h RO,R/W F0h RO,R/W 00h RO,R/W 02A0h RO,R/WC FFF0h RO,R/W 0000h RO,R/W FFF0h RO,R/W 0000h RO,R/W — — 00h RO,R/W — — 00h RO,R/W — — 0E04 2802h RO,R/W — — ® Intel 82875P MCH Datasheet ...
Page 93
... The VID Register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register, uniquely identify any PCI device. Bit 15:0 Vendor Identification Number—RO. This is a 16-bit value assigned to Intel. 3.7.2 DID3—Device Identification Register (Device 3) Address Offset: ...
Page 94
... Fast Back-to-Back (FB2B)—RO. Hardwired to 0. SERR# Enable (SERRE)—R/W. This bit is a global enable bit for Device 3 SERR messaging. The MCH communicates the SERR# condition by sending a SERR message to the Intel 0 = Disable. The SERR message is not generated by the MCH for Device 3. ...
Page 95
... This register contains the revision number of the MCH Device 3. Bit Revision Identification Number—RO. This is an 8-bit value that indicates the revision identification number for the MCH Device always the same as the value in RID. 7:0 02h = A-2 Stepping ® Intel 82875P MCH Datasheet 06h−07h 00A0h RO, R/WC 16 bits Description ...
Page 96
... Scratchpad MLT (NA7:3)—R/W. These bits return the value with which they are written; however, 7:3 they have no internal function and are implemented as a scratchpad merely to avoid confusing software. 2:0 Reserved 96 0Ah 04h RO 8 bits Description 0Bh 06h RO 8 bits Description 0Dh 00h RO bits Description ® Intel 82875P MCH Datasheet ...
Page 97
... CSA). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to CSA. Bit Secondary Bus Number (BUSN)—R/W. This field is programmed by configuration software with 7:0 the bus number assigned to CSA. ® Intel 82875P MCH Datasheet 0Eh 01h RO 8 bits Description ...
Page 98
... Bit I/O Address Base (IOBASE)—R/W. This field corresponds to A[15:12] of the I/O addresses 7:4 passed by bridge 1 to CSA. 3:0 Reserved 98 1Bh 00h RO 8 bits. Description 1Ch F0h RO, R/W 8 bits IO_BASE ≤ address ≤ IO_LIMIT Description ® Intel 82875P MCH Datasheet ...
Page 99
... Bit I/O Address Limit (IOLIMIT)—R/W. This field corresponds to A[15:12] of the I/O address limit of 7:4 Device 3. Devices between this upper limit and IOBASE3 will be passed to CSA. 3:0 Reserved ® Intel 82875P MCH Datasheet 1Dh 00h RO bits Description Register Description ...
Page 100
... CSA. Fast Back-to-Back (FB2B)—RO. Hardwired to 1. MCH target, supports fast back-to-back 7 transactions on CSA. 6 Reserved 5 66/60 MHz PCI Capable (CAP66)—RO. Hardwired to 1. CSA is 66 MHz capable. 4:0 Reserved 100 1E–1Fh 02A0h RO, RWC 16 bits Description ® Intel 82875P MCH Datasheet ...
Page 101
... Bit Memory Address Limit (MLIMIT)—R/W. This field corresponds to A[31:20] of the lower limit of the 15:4 memory range that will be passed by Device 3 bridge to CSA. 3:0 Reserved ® Intel 82875P MCH Datasheet 20–21h FFF0h RO bits Description Register Description ...
Page 102
... Memory Address Limit (MLIMIT)—R/W. This field corresponds to A[31:20] of the memory address 15:4 that corresponds to the upper limit of the range of memory accesses that will be passed by the Device 3 bridge to CSA. 3:0 Reserved 102 22–23h 0000h RO, R/W 16 bits Description ® Intel 82875P MCH Datasheet ...
Page 103
... Bit Prefetchable Memory Address Limit (PMLIMIT)—R/W. This field corresponds to A[31:20] of the 15:4 upper limit of the address range passed by bridge Device 3 across CSA. 3:0 Reserved ® Intel 82875P MCH Datasheet 24−25h FFF0h R/ bits Description 26−27h 0000h ...
Page 104
... All References to MDA and VGA space are routed to HI. 1 Illegal combination. 0 All VGA references are routed to this bus. MDA references are routed to HI. 1 All VGA references are routed to this bus. MDA references are routed to HI. Table 11. Description ® Intel 82875P MCH Datasheet ...
Page 105
... Last Subordinate CSA (CSA_SUB_LAST)—R/W. This field stores the highest subordinate CSA 27:25 hub number. 24:16 Reserved CSA Width (CSA_WIDTH)—R/W. This field describes the used width of the data bus bit 15: Reserved 10 = Reserved 11 = Reserved 13:0 Intel Reserved ® Intel 82875P MCH Datasheet 40h 00h R/ bits Description 50–53h 0E042802h R/W, RO ...
Page 106
... PCI Command Register PCI Status Register Revision Identification Reserved Sub-Class Code Base Class Code Reserved Header Type Reserved Base Address Reserved Subsystem Vendor Identification Subsystem Identification Reserved Intel Reserved 00–01h 8086h RO 16 bits Descriptions Default Value Access 8086h RO 257Eh RO 0000h RO, R/W ...
Page 107
... Disable (default Enable. I/O Access Enable (IOAE)—R/W. This bit must be set enable the I/O address range defined in the IOBASE3 and IOLIMIT3 registers Disable (default Enable. ® Intel 82875P MCH Datasheet 02–03h 257Eh RO 16 bits Descriptions 04–05h 0000h RO, R/W 16 bits ...
Page 108
... Revision Identification Number (RID)—RO. This is an 8-bit value that indicates the revision identification number for the MCH Device 6. 7:0 02h = A-2 Stepping 108 06–07h 0080h RO 16 bits Descriptions 08h See following table RO 8 bits Descriptions ® Intel 82875P MCH Datasheet ...
Page 109
... Address Offset: Default Value: Access: Size: This register identifies the header layout of the configuration space. Bit PCI Header (HDR)—RO. 7:0 00h = Single function device with standard header layout. ® Intel 82875P MCH Datasheet 0Ah 80h RO 8 bits Descriptions 0Bh 08h RO ...
Page 110
... Bit Subsystem ID (SUBID)—R/WO. This field should be programmed during BIOS initialization. After it 15:0 has been written once, it becomes read only. 110 10–13h 00000000h RO, R/W 32 bits Descriptions 2C–2Dh 0000h R/WO 16 bits Descriptions 2E–2Fh 0000h R/WO 16 bits Descriptions ® Intel 82875P MCH Datasheet ...
Page 111
... DRAM Row 4,5 Attribute DRAM Row 6,7 Attribute — Intel Reserved DRT DRAM Timing — Intel Reserved DRC DRAM Controller Mode — Intel Reserved 0000h–0007h (DRB0–DRB7) 00h RO, R/W 8 bits each register Register Description Default Value Access 01h RO, RW 01h ...
Page 112
... DRAM Row Boundary Address—R/W. This 7-bit value defines the upper and lower addresses for each DRAM row. This 7-bit value is compared against address lines 0, 31: concatenated with 6:0 the address bits 31:26) to determine which row the incoming address is directed. Default= 0000001b 112 Description ® Intel 82875P MCH Datasheet ...
Page 113
... Row Attribute for Even-Numbered Row—R/W. This field defines the page size of the corresponding row. If the associated row is not populated, this field must be left at the default value. 000 = 4 KB 2:0 001 = 8 KB 010 = 16 KB 011 = 32 KB Others = Reserved ® Intel 82875P MCH Datasheet 0010h 0013h — 00h RO, R/W 8 bits each register 4 ...
Page 114
... This register controls the timing of micro-commands. When in virtual single-channel mode, the timing fields specified here apply even if two back-to-back cycles are to different physical channels. That is, the controller acts as if the two cycles are to the same physical channel. Bit 31:11 Intel Reserved Activate to Precharge delay (t t maximum. RAS 0 = 120 µ ...
Page 115
... BIOS BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. 28 Reserved 27:23 Intel Reserved Number of Channels (CHAN)—RO. This field reflects that the MCH controller supports two modes of operation Single-channel or virtual single-channel 22: Dual-channel ...
Page 116
... Reserved 110 = CBR Refresh Enable – In this mode all processor cycles to DRAM result in a CBR cycle on the DRAM interface 111 = Normal operation 3:2 Intel Reserved DRAM Type (DT)—RO. This field is used to select between supported DRAM types Reserved 1 Dual data rate DRAM ...
Page 117
... BIOS or system designers responsibility to limit memory population so that adequate PCI, AGP, High BIOS, and APIC memory space can be allocated. system memory address map. regions as defined and supported by the MCH. ® Intel 82875P MCH Datasheet Figure 9 Figure 10 provides additional details on mapping specific memory ...
Page 118
... Memory Range Main Memory Address Independently Programmable Range Non-Overlapping 0 Memory Windows 4 GB Max Top of the Main Memory FLASH APIC Reserv ed TOP of DRAM Intel Reserv ed TOUD(OS Visible Main Memory Optional ISA Hole Optionally mapped to the internal AGP 640 AGP Graphics Address (AGP) ...
Page 119
... Intel 82875P MCH Datasheet Attributes Fixed: always mapped to main 0 to 640 KB – DOS Region DRAM Video Buffer (physical DRAM Mapped to Hub Interface, AGP configurable as SMM space) ...
Page 120
... This area is a single, 64-KB segment. This segment can be assigned read and write attributes default (after reset) read/write disabled and cycles are forwarded to hub interface. By manipulating the read/write attributes, the MCH can “shadow” BIOS into the main system memory. When disabled, this segment is not remapped. 120 ® Intel 82875P MCH Datasheet ...
Page 121
... Top of the memory – that physical system memory space is not accessible. This 15-MB–16-MB hole is an optionally enabled ISA hole. Video accelerators originally used this hole. There is no inherent BIOS request for the 15-MB–16-MB hole. ® Intel 82875P MCH Datasheet System Address Map 121 ...
Page 122
... As a memory controller hub, there is one exception to this rule. • Addresses decoded to MMIO for DRAM RCOMP configuration registers. 122 Attributes R/W Available System Memory 62.5 MB SMM Mode Only - processor TSEG Address Range Reads SMM Mode Only - processor TSEG Pre-allocated Memory Reads Intel Comments ® 82875P MCH Datasheet ...
Page 123
... MB–256 KB range. The actual address space required for the BIOS is less than 2 MB but the minimum processor MTRR range for this region that full 2 MB must be considered. ® Intel 82875P MCH Datasheet System Address Map 123 ...
Page 124
... PCI devices. The PCICMD1 register can override the routing of memory accesses to AGP. In other words, the memory access enable bit must be set in the Device 1 PCICMD1 register to enable the memory base/limit and prefetchable base/limit windows. 124 ® Intel 82875P MCH Datasheet ...
Page 125
... FSB Overview The MCH supports the Intel size is 64 bytes. Source synchronous transfer is used for the address and data signals. At 100 MHz, 133 MHz, or 200 MHz bus clock, the address signals are double pumped to run at 200 MHz, 266 MHz, or 400 MHz and a new address can be generated every other bus clock ...
Page 126
... FSB Interrupt Overview Intel processors support FSB interrupt delivery. They do not support the APIC serial bus interrupt delivery mechanism. Interrupt-related messages are encoded on the FSB as “Interrupt Message Transactions.” In the 875P chipset platform, FSB interrupts may originate from the processor on the system bus, or from a downstream device on the hub interface or AGP ...
Page 127
... Any correctable (single-bit) errors detected during the initial QWord read are corrected before merging the new DWord. DIMM Population Guidelines DIMM population guidelines are shown in Figure 11. Single-Channel Mode Operation CH A MCH Mode Only ® Intel 82875P MCH Datasheet Smallest Largest Increments Increments 64 MB 256 MB 128 MB 512 MB ...
Page 128
... Page-coloring addressing is modified, now called “Address-MUXING-dynamic mode,” only enabled when the following population rules are met. • Population rules - Applicable to dynamic mode: • Single-/dual-channel mode 1 pair, 2 pairs pairs of identical ranks are populated 128 CH A MCH MCH DIMMs ® Intel 82875P MCH Datasheet DIMMs ...
Page 129
... Dynamic addressing mode minimizes the overhead of opening/closing pages in memory banks allowing for row switching to be done less often. ® Intel 82875P MCH Datasheet Dynamic Addressing Mode 1 Channel A Only ...
Page 130
... Technology 512 Mbit – 64Mx8 – page size – row size of 512 MB Note: In Table 18 through The table cell contents refers to host address signals HAx. 130 Table 21 A0, A1, … refers to memory address MA0, MA1, …. Table 18 through Table 21. The Section 5.2.5 for ® Intel 82875P MCH Datasheet ...
Page 131
... KB Col 128 MB Row 256Mb 16Mx16 13x9x2 4 KB Col 256 MB Row 256Mb 32Mx8 13x10x2 8 KB Col 256 MB Row 512Mb 32Mx16 13x10x2 8 KB Col 512 MB Row 512Mb 64Mx8 13x11x2 16 KB Col ® Intel 82875P MCH Datasheet Addr BA1 BA0 A12 A11 A10 ...
Page 132
... KB Col 256 MB Row 256Mb 32Mx8 13x10x2 8 KB Col 256 MB Row 512Mb 32Mx16 13x10x2 8 KB Col 512 MB Row 512Mb 64Mx8 13x11x2 16 KB Col 132 Addr BA1 BA0 A12 A11 A10 Addr BA1 BA0 A12 A11 A10 ® Intel 82875P MCH Datasheet ...
Page 133
... Note that the MCH 128 Mbit 256 Mbit X8 X16 X8 SS/DS SS/DS SS/DS 128/256 MB 64 MB/NA 256/512 MB ® 82801EB I/O Controller Hub 5 (ICH5) and Intel Functional Description 512 Mbit X16 X8 X16 SS/DS SS/DS SS/DS 128 MB/NA 512/1024 MB 256 MB/NA ® ...
Page 134
... MCH. 5.2.7.1 Determining When to Thermal Manage Thermal management may be enabled by one of two mechanisms: • Software forcing throttling via the SRT (SWT) bit. • Counter Mechanism. 134 Table 23 lists a subset of the Function ® Intel 82875P MCH Datasheet ...
Page 135
... An AGP 2.0 card puts the system into AGP 2.0. An AGP 3.0 card puts the system into AGP 3.0 mode. The mode is selected during RESET by a hardware mechanism that is described in Section dynamically changed once the system powers up. ® Intel 82875P MCH Datasheet AGP 3.0 AGP 2 4X ...
Page 136
... GC/BE# GC#/BE Strobe StrobeFirst Strobe# StrobeSecond No Disabled on xmit Yes No AGP 2.0 commands AGP 3.0 commands No (Not supported) No Yes Intel AGP 3.0 Signaling (8X Data Rate) 8X 0.35 V 3.0 signaling (0.8 V swing) Active high inverted (000 = idle) GC#/BE StrobeFirst StrobeSecond Yes No AGP 3.0 commands No Yes ® ...
Page 137
... Long Read (High Priority) 1010 Flush (Low Priority) 1011 Reserved 1100 Fence (Low Priority) 1101 Reserved (was DAC cycle) 1110 Reserved 1111 Reserved ® Intel 82875P MCH Datasheet Pull-up/ AGP 3.0 Detect GPAR Value on PWROK Assertion of PWROK pull- APG 2.0 Command Read (Asynchronous) Reserved ...
Page 138
... The 8X data transfer protocol provides 2.1 GB/s transfer rates mode, 32 bytes of data are transferred during each 66 MHz clock period. The minimum throttleable block size remains four 66 MHz clocks which means 128 bytes of data is transferred per block. 138 Signaling Level 1.5 V 3.3 V Yes No Yes No See Note No Yes ® Intel 82875P MCH Datasheet ...
Page 139
... G0/S0 — G1/S1 — G1/S2 — G1/S3 — G1/S4 — G2/S5 — G3 ® Intel 82875P MCH Datasheet Full On. Auto Halt. Stop Grant. Clock to processor still running. Clock stopped to processor Full On. Stop Grant, Desktop S1, same as C2. Not supported. Suspend to RAM (STR). Power and context lost to chipset. ...
Page 140
... DIMMs will be located on the same memory bus data lines, any MCH-base read throttle will apply equally. Note: The use of external sensors that include an internal pull-up resistor on the open-drain thermal trip output is discouraged; however, it may be possible depending on the size of the pull-up and the voltage of the sensor. 140 ® Intel 82875P MCH Datasheet ...
Page 141
... Characterization tools (e.g., CTMI and Maxband) can be made to work either with external or internal sensors. ® Intel 82875P MCH Datasheet ETS# MCH THERM Intel ® ICH5 SMBus Functional Description V R (1) SMBdata SMBclock 141 ...
Page 142
... These pins receive a host clock from the external clock synthesizer. This clock is used by the host interface and system memory logic (Host Clock Domain). AGP and hub interface are synchronous to each other and are driven off of the 66-MHz clock. ® Figure 14. Intel 875P Chipset System Clock Block Diagram Low Voltage Differential Clocks Low Voltage Differential Clocks ...
Page 143
... VCCA_AGP VCC_HI VTT VCC_DDR VCCA_DDR VCC_33 VCCA_FSB 6.2 Thermal Characteristics ® Refer to the Intel ® Intel 82875P MCH Datasheet Parameter 1.5 V Core Supply 1.5 V AGP Supply 1.5 V Analog AGP Supply 1.5 V HI/CSA Supply VTT Supply 2.6 V DDR System Memory Interface Supply 1 ...
Page 144
... GADSTBF[1:0], GADSTBS[1:0], GFRAME, GIRDY, GTRDY, GSTOP, GDEVSEL, GAD[31:0], GCBE[3:0], GPAR, DBI_HI, DBI_LO GSBA[7:0]#, GRBF, GWBF, GSBSTBF, GSBSTBS, GREQ GST[2:0], GGNT GVREF, GRCOMP, GVSWING Max Unit Notes 2 0. 0. 1.6 A 6.27 A 1.2 A 0.2 A 0.05 A 0.250 A 1 Notes ® Intel 82875P MCH Datasheet ...
Page 145
... XOR Test pins (x) Bus Select Inputs (y) Clock pin NOTES: 1. For details on BSEL[1:0] pin electrical requirements, see the Intel 2. For additional details on SMXRCOMP, SMYRCOMP, SMXRCOMPVOL, SMXRCOMPVOH, SMYRCOMPVOL, SMYRCOMPVOH pin electrical requirements see the Intel Design Guide. ® Intel 82875P MCH Datasheet Signals ...
Page 146
... VccCPU)/2 VccCPU_min)/2 0.63 x Vsh_min – 2% 0.63 x Vsh Max Unit 1.575 V 1.575 V 1.575 V 1.575 V 1.55 V 1.31 V 2.7 V 1.575 V 3.465 V 1.575 V 1/2 * VCC_AGP_max 0.2333* VCC_AGP_max V +0.01 0.5333*VCC_AGP_max V + 0.05 0.357 V 0.816 V 0.357 V 0.816 V (Vtt_max + V VccCPU_max)/2 0.63 x Vsh_max + 2% V ® Intel 82875P MCH Datasheet ...
Page 147
... AC noise components > 20 MHz, the maximum allowable noise component at the MCH is ±180 mV at VCC_nom, +180/-105 mV at VCC_min, and +105/-180 mV at VCC_max. For AC noise components < 20 MHz, the sum of the DC voltage and AC noise component must be within the specified DC minimum/ maximum operating range. ® Intel 82875P MCH Datasheet Min Nom 1/4 x Vtt_min – 2% ...
Page 148
... 0.1* 6.65 mA VCC_AGP @ 0.85* mA VCC_AGP 0<Vin< ±25 µA VCC_AGP =1MHz C V VCC_AGP V = 1500 µA 0. out 0.5333* Standard 50 Ω V load to ground +0.05 17.78 mA ±25 µA 2 MHz C V 1 0.8/R , OUT TT 1 Ω ± 50 µ =1MHz C ® Intel 82875P MCH Datasheet ...
Page 149
... OL_DDR Current DDR Output High I (l,m) OH_DDR Current I DDR RCOMP Output OL_DDR (v) Low Current RCOMP ® Intel 82875P MCH Datasheet Min Nom –0.3 CI_VREF – 0.1 CI_VREF + 0.1 0.6 HDVREF + (0.04*Vsh) 1/4* Vsh (Vsh–0.1) * 0.95 0.75 * Vshmax / 1 –0.1 * VCC_DDR SMVREF – ...
Page 150
... Chipset Platform Design Guide for the resistor divider circuit details that take this specification into account. 8. Maximum leakage current specification for CI_VREF and CI_SWING pins is 50 µA. Refer to the Intel Chipset Platform Design Guide for the resistor divider circuit details that takes this specification into account. ...
Page 151
... For AGP signals, only the AGP 2.0 signal name is listed. For the corresponding AGP 3.0 signal name, refer Connect. 3. RSVD = These reserved balls should not be connected and should be allowed to float. 4. Shaded cells in ® Intel 82875P MCH Datasheet Figure 15 and Figure 16. These figures represent the ballout Table 34 provides the ballout arranged alphabetically by signal name ...
Page 152
... HDSTB VSS VSS VSS HD55# P1# N3# HDSTB HD31# HD50# HD52# HD51# HD54# N1# HDSTB VSS HD40# VSS HD46# VSS P2# HD37# HD38# DINV2# HD45# HD44# HA18# VSS HD41# VSS HD43# VSS HA19# HD39# HD35# VTT HD42# HD47# HA17 ® Intel 82875P MCH Datasheet ...
Page 153
... HA29# VSS RS0# BSEL1 BSEL0 BPRI# HA22# HA30# VSS HA28# VSS BNR# VSS VTT HA25# HA23# HA24# HDRCOMP ® Intel 82875P MCH Datasheet RSVD VCC_HI HI7 VSS HI6 VSS CI2 HI5 HI8 CI1 VSS CISTRF VSS CISTRS VSS CI3 CI10 CI8 ...
Page 154
... HA6# H12 HA7# F11 P1 HA8# E9 HA9# F9 HA10 HA11# G8 HA12# H10 V2 HA13# J11 HA14# J7 HA15# F7 HA16 HA17# A17 HA18# C17 HA19# B17 HA20# B11 T6 HA21# C9 HA22# C13 HA23# A14 V7 HA24# A13 HA25# A15 T5 HA26 HA27 HA28# B15 ® Intel 82875P MCH Datasheet ...
Page 155
... HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# ® Intel 82875P MCH Datasheet Table 34. MCH Ballout by Signal Name Ball # Signal Name Ball # D14 HD35# A21 C12 HD36# D24 C7 HD37# C22 G9 HD38# C21 ...
Page 156
... SDQ_A55 H31 SDQ_A56 F33 SDQ_A57 F31 SDQ_A58 D31 SDQ_A59 E31 SDQ_A60 G32 SDQ_A61 G31 SDQ_A62 E33 SDQ_A63 E32 SDQ_B0 AG14 SDQ_B1 AL13 SDQ_B2 AK14 SDQ_B3 AJ15 SDQ_B4 AJ13 SDQ_B5 AM13 SDQ_B6 AJ14 SDQ_B7 AH15 SDQ_B8 AG15 ® Intel 82875P MCH Datasheet ...
Page 157
... SDQ_B35 SDQ_B36 SDQ_B37 SDQ_B38 SDQ_B39 SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47 SDQ_B48 SDQ_B49 SDQ_B50 ® Intel 82875P MCH Datasheet Table 34. MCH Ballout by Signal Name Ball # Signal Name Ball # AG16 SDQ_B51 L25 AK18 SDQ_B52 P29 AE19 SDQ_B53 N28 AJ16 SDQ_B54 ...
Page 158
... VCC_AGP J4 VCC_AGP J3 VCC_AGP J2 P9 VCC_AGP J1 VCC_AGP H3 VCC_AGP H2 VCC_AGP H1 VCC_AGP G3 VCC_AGP G2 VCC_AGP G1 VCC_AGP F1 VCC_DDR AN30 VCC_DDR AN22 VCC_DDR AN18 VCC_DDR AN11 VCC_DDR AN10 VCC_DDR AM12 L9 VCC_DDR AM11 L8 VCC_DDR AM10 L7 VCC_DDR AL12 L6 VCC_DDR AL11 L5 VCC_DDR AL10 K6 VCC_DDR AK12 ® Intel 82875P MCH Datasheet ...
Page 159
... VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR ® Intel 82875P MCH Datasheet Table 34. MCH Ballout by Signal Name Ball # Signal Name Ball # AK11 VCC_DDR T24 AK10 VCC_DDR R23 AJ12 VCC_DDR P33 AJ11 VCC_DDR ...
Page 160
... F16 VSS F14 VSS F12 VSS F10 VSS F8 VSS F6 VSS F3 VSS E30 VSS E2 V8 VSS D32 V4 VSS D30 VSS D29 VSS D27 VSS D25 VSS D23 VSS D21 VSS D19 VSS D17 VSS D15 VSS D13 ® Intel 82875P MCH Datasheet ...
Page 161
... VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ® Intel 82875P MCH Datasheet Table 34. MCH Ballout by Signal Name Ball # Signal Name Ball # D11 VSS P17 D9 VSS P15 D7 VSS D1 VSS C31 VSS ...
Page 162
... Ballout and Package Information 7.2 Package Information The MCH 42 42.5 mm Flip Chip Ball Grid Array (FC-BGA) package with 1005 solder balls and 1 mm ball pitch. Figure 17 ® Figure 17. Intel 82875P MCH Package Dimensions (Top View) Handling Exclusion Area 0.583in. ® Figure 18. Intel 82875P MCH Package Dimensions (Side View) 2.020 ± ...
Page 163
... Figure 19. Intel 82875P MCH Package Dimensions (Bottom View Solder Resist Opening Detail A (n)x 0.650 ± 0.040 Metal Edge (n)x ∅ 0.790 ± 0.025 (n)x 0.025 Min NOTES: 1. All dimensions are in millimeters 2. All dimensions and tolerances conform to ANSI Y14.5M–1982 ® ...
Page 164
... Ballout and Package Information 164 This page is intentionally left blank. ® Intel 82875P MCH Datasheet ...
Page 165
... XOR operation. This applies to AGP 2.0 mode. If the part is in AGP 3.0 mode, GSBA6,# GSBA7#, and GC#/BE1 must be driven high. Figure 20. XOR Toggling of HCLKP and HCLKN PWROK TESTIN# GSBA6 GFRAME# RSTIN# GCLKIN HCLKP HCLKN ® Intel 82875P MCH Datasheet Testability Figure 165 ...
Page 166
... Figure 21. XOR Testing Chains Tested Sequentially PWROK TESTIN# RSTIN# GSBA6 GFRAME# GCLKIN HCLKP HCLKN DREFCLK SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 HTRDY# RS2# RS0# BREQ0# 166 Figure 21 shows chains are tested Intel ® 82875P MCH Datasheet ...
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... The channel A and channel B output pins for each chain show the same output. 3. For AGP signals, only the AGP 3.0 signal name is listed. For the corresponding AGP 2.0 signal name, refer to ® Intel 82875P MCH Datasheet DDR Output Pin Channel A TESTP17 ...
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... GAD14 AC4 GSBA5# GTRDY AB1 GSBA3# GPAR AB3 GSBA4# GCBE1 AC5 GSBA1# GFRAME AB7 GSBA6# DBI_LO P2 TESTP2 GDEVSEL AB2 TESTP3 GRBF V7 TESTP0 GWBF U5 RSVD Intel Signal Name Ball Number U7 AB6 AA3 AA7 AA8 V6 AA5 K9 K8 K11 AC7 ® 82875P MCH Datasheet ...
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... H23 HD30# E23 HD20# G26 DINV1# F25 HD23# G25 HDSTBP1# F21 HDSTBN1# E22 Output Pins TESTP19 AH20 TESTP6 AH26 ® Intel 82875P MCH Datasheet Signal Name Ball Number HI8 AL7 GAD23 HI9 AN4 GAD25 GST1 U8 GAD27 GAD20 Y3 GAD24 GAD16 AA4 GAD21 ...
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... HD56# G16 HD53# HD62# G17 HD50# HD61# H16 HD48# HD63# E15 HD52# HD59# J15 DINV3# HD60# E14 GADSTBF1 TESTP1 Intel Signal Name Ball Number B17 C17 C13 A13 A14 D16 A17 A15 B11 C12 C9 C8 D14 B15 Signal Name Ball Number ...
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... SDQ_A24 AN29 SDQ_A28 AJ27 SDQS_A2 AL25 SDQ_A21 AM25 SDQ_A17 AN25 SDQ_A18 AK26 Output Pins TESTP23 L30 TESTP10 R26 ® Intel 82875P MCH Datasheet Signal Name Ball Number SDQ_A53 K33 SDQ_A41 SDQ_A48 L31 SDQ_A44 SDQ_A52 L33 SDQS_A4 SDQ_A49 L32 SDQ_A35 SCMDCLK_A5# K31 ...
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... SDQ_B15 AJ18 SDQ_B7 SDQ_B11 AE19 SDQ_B2 SDQ_B13 AE17 SDQ_B6 SDQ_B12 AJ16 SDQ_B5 SDQ_B9 AG16 SDQ_B0 SDQS_B1 AF16 SDQ_B4 SDQS_B0 Intel Signal Name Ball Number T26 R28 Y29 Y27 V27 Y26 W27 W28 AA29 W29 W25 AE29 AD29 AD27 AC27 Signal Name ...
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... Table 46. XOR Chain 10 (9 Inputs) Output Pins: RS0#, RS1# Signal Name Ball Number SECC_A5 AH33 SECC_A4 AJ33 SECC_A2 AE33 Output Pins RS0# D12 RS1# G10 ® Intel 82875P MCH Datasheet Signal Name Ball Number SMAA_B0 AB26 SMAA_B7 TESTP25 AC26 SMAA_B9 SMAA_A6 AK28 SMAA_B11 SMAA_B6 AG25 ...
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... TESTP10 R26 TESTP11 N26 SMVREF_A C32 SMVREF_B AN12 SMXRCOMP AG13 SMXRCOMPVOH AN13 SMXRCOMPVOL AH13 SMYRCOMP AD31 SMYRCOMPVOH N32 SMYRCOMPVOL N33 RESERVED A5 TESTIN# AC9 CI_RCOMP AF2 CI_VREF AG1 CI_SWING AE3 Intel Signal Name Ball Number AA27 AC25 AB27 ® 82875P MCH Datasheet ...