JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 102

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.7.17
102
Note: Memory ranges covered by MBASE and MLIMIT registers are used to map non-prefetchable CSA
Note: Configuration software is responsible for programming all address range registers (prefetchable,
MLIMIT3—Memory Limit Address Register (Device 3)
Address Offset:
Default Value:
Access:
Size:
This register controls the processor-to-CSA non-prefetchable memory access routing based on the
following formula:
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom four bits of this register are read only and return 0’s
when read. This register must be initialized by the configuration software. For the purpose of
address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1-MB aligned memory block.
address ranges (typically, where control/status memory-mapped I/O data structures of the graphics
controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address ranges
(typically, graphics local memory). This segregation allows application of USWC space attribute to
be performed in a true plug-and-play manner to the prefetchable address range for improved
processor-CSA memory access performance.
non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with
each other and/or with the ranges covered with the main memory). There is no provision in the
MCH hardware to enforce prevention of overlap and operations of the system in the case of overlap
are not guaranteed.
15:4
3:0
Bit
Memory Address Limit (MLIMIT)—R/W. This field corresponds to A[31:20] of the memory address
that corresponds to the upper limit of the range of memory accesses that will be passed by the
Device 3 bridge to CSA.
Reserved
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
22–23h
0000h
RO, R/W
16 bits
Description
Intel
®
82875P MCH Datasheet