JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 83

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.6.8
3.6.9
3.6.10
Intel
®
82875P MCH Datasheet
MLT1—Master Latency Timer Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This functionality is not applicable. It is described here since these bits should be implemented as
read/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.”
HDR1—Header Type Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This register identifies the header layout of the configuration space. No physical register exists at
this location.
PBUSN1—Primary Bus Number Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This register identifies that “virtual” PCI-to-PCI bridge is connected to bus 0.
7:3
2:0
7:0
7:0
Bit
Bit
Bit
Scratchpad MLT (NA7.3)—R/W. These bits return the value with which they are written; however,
they have no internal function and are implemented as a scratchpad merely to avoid confusing
software.
Reserved
Header Type Register (HDR)—RO. This read only field always returns 01 to indicate that MCH
Device 1 is a single function device with bridge header layout.
Primary Bus Number (PBUSN—RO. Configuration software typically programs this field with the
number of the bus on the primary side of the bridge. Since Device 1 is an internal device and its
primary bus is always 0, these bits are read only and are hardwired to 0.
0Dh
00h
RO, R/W
8 bits
0Eh
01h
RO
8 bits
18h
00h
RO
8 bits
Descriptions
Descriptions
Descriptions
Register Description
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