JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 46

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.5
46
Table 6.
DRAM Controller/Host-Hub Interface Device
Registers (Device 0)
This section contains the DRAM Controller and Host-Hub Interface PCI configuration registers
listed in order of ascending offset address. The register address map is shown in
DRAM Controller/Host-Hub Interface Device Register Address Map (Device 0)
Address
2C–2Dh
2E–2Fh
5E–5Fh
00–01h
02–03h
04–05h
06–07h
10–13h
14–2Bh
30–33h
35–50h
54–57h
58–5Bh
61–89h
Offset
0Ah
0Bh
0Dh
0Eh
5Ch
5Dh
08h
09h
0Fh
34h
51h
52h
53h
60h
90h
91h
92h
93h
0C
CSABCONT
FPLLCONT
DERRSYN
Register
PCICMD
APBASE
CAPPTR
Symbol
PCISTS
AGPM
SUBC
PAM0
PAM1
PAM2
PAM3
SVID
BCC
HDR
EAP
DES
MLT
DID
RID
VID
SID
GC
—
—
—
—
—
—
—
—
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Intel Reserved
Sub-Class Code
Base Class Code
Intel Reserved
Master Latency Timer
Header Type
Intel Reserved
Aperture Base Configuration
Intel Reserved
Subsystem Vendor Identification
Subsystem Identification
Intel Reserved
Capabilities Pointer
Intel Reserved
AGP Miscellaneous Configuration
Graphics Control
CSA Basic Control
Intel Reserved
DRAM Error Data Register
DRAM Error Syndrome
DRAM Error Status
Intel Reserved
FPLL Clock Control
Intel Reserved
Programmable Attribute Map 0
Programmable Attribute Map 1
Programmable Attribute Map 2
Programmable Attribute Map 3
Register Name
Intel
Default Value
0000_1000b
0000_000sb
see register
00000008h
description
undefined
undefined
undefined
8086h
2578h
0006h
0090h
0000h
0000h
E4h
00h
06h
00h
00h
00h
00h
00h
00h
00h
00h
®
—
—
—
—
—
—
—
—
82875P MCH Datasheet
Table
RO, R/WC
RO, R/W
RO, R/W
RO, R/W
R/W, RO
RO, R/W
RO, R/W
RO, R/W
RO, R/W
6.
Access
R/WO
R/WO
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
—
—
—
—
—
—
—