JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 6

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

4
5
6
3.9
System Address Map
4.1
4.2
4.3
4.4
Functional Description
5.1
5.2
5.3
3.8.7
3.8.8
3.8.9
3.8.10 SVID6—Subsystem Vendor Identification Register
3.8.11 SID6—Subsystem Identification Register (Device 6)...................... 110
Device 6 Memory-Mapped I/O Register Space ........................................... 111
3.9.1
3.9.2
3.9.3
3.9.4
System Memory Address Ranges ............................................................... 117
Compatibility Area........................................................................................ 119
Extended Memory Area ............................................................................... 121
4.3.1
4.3.2
AGP Memory Address Ranges.................................................................... 124
Processor System Bus ................................................................................ 125
5.1.1
5.1.2
5.1.3
System Memory Controller .......................................................................... 127
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
Accelerated Graphics Port (AGP) ................................................................ 135
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
BCC6—Base Class Code Register (Device 6) ............................... 109
HDR6—Header Type Register (Device 6) ...................................... 109
BAR6—Memory Delays Base Address Register (Device 6)........... 110
(Device 6) ....................................................................................... 110
DRB[0:7]—DRAM Row Boundary Registers (Device 6, MMR) ...... 111
DRA— DRAM Row Attribute Register (Device 6, MMR) ................ 113
DRT—DRAM Timing Register (Device 6, MMR) ............................ 114
DRC—DRAM Controller Mode Register (Device 6, MMR) ............. 115
15-MB–16-MB Window................................................................... 121
Pre-Allocated Memory .................................................................... 122
FSB Overview................................................................................. 125
FSB Dynamic Bus Inversion ........................................................... 125
FSB Interrupt Overview .................................................................. 126
5.1.3.1
DRAM Technologies and Organization........................................... 128
Memory Operating Modes .............................................................. 129
5.2.2.1
Single-Channel (SC) Mode ............................................................. 130
5.2.3.1
Memory Address Translation and Decoding................................... 130
Memory Organization and Configuration ........................................ 133
Configuration Mechanism for DIMMS ............................................. 133
5.2.6.1
5.2.6.2
5.2.6.3
Memory Thermal Management....................................................... 134
5.2.7.1
MCH AGP Support ......................................................................... 135
Selecting between AGP 3.0 and AGP 2.0 ...................................... 135
AGP 3.0 Downshift (4X Data Rate) Mode....................................... 136
5.3.3.1
AGP Target Operations .................................................................. 137
AGP Transaction Ordering ............................................................. 138
Support for PCI-66 Devices ............................................................ 138
8X AGP Protocol............................................................................. 138
5.3.7.1
5.3.7.2
Upstream Interrupt Messages ......................................... 126
Dynamic Addressing Mode ............................................. 129
Linear Mode .................................................................... 130
Memory Detection and Initialization ................................ 133
SMBus Configuration and Access of the Serial
Presence Detect Ports .................................................... 133
Memory Register Programming ...................................... 134
Determining When to Thermal Manage .......................... 134
Mechanism for Detecting AGP 2.0 and AGP 3.0 ............ 136
Fast Writes ...................................................................... 139
PCI Semantic Transactions on AGP ............................... 139
...................................................................................... 117
................................................................................... 125
Intel
®
82875P MCH
Datasheet