JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 36

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Signal Description
2.10
2.10.1
2.10.2
2.10.3
36
Signals Used As Straps
Functional Straps
NOTE:
Strap Input Signals
Test Mode Straps
1. All straps, have internal 8 kΩ pull-ups (HA7# has GTL pull-up) enabled during their sampling window.
HA7#
Signal Name
BSEL[1:0]
GSBA7
GSBA6
Signal Name
Signal
Therefore, a strap that is not connected or not driven by external logic will be sampled high.
Name
XOR Chain Test Mode
CMOS
Type
Strap Name
FSB IOQ Depth
I
Strap Name
All Z
Core / FSB Frequency (FSBFREQ) Select Strap: This strap is latched at the
rising edge of PWROK. These pins has no default internal pull-up resistor.
00 = Core frequency is 100 MHz, FSB frequency is 400 MHz
01 = Core frequency is 133 MHz, FSB frequency is 533 MHz
10 = Core Frequency is 200 MHz, FSB frequency is 800 MHz
11 = Reserved
The value on HA7# is sampled by all processor bus agents, including
the MCH, on the de-asserting edge of CPURST#.
NOTE: For HA7# the minimum setup time is 4 HCLKs. The minimum
The latched value determines the maximum IOQ depth supported on
the processor bus.
• 0 (low voltage) = BUS IOQ depth on the bus is 1
• 1 (high voltage) = BUS IOQ depth on the bus is the maximum of 12
AGP 2.0: Strap Sampled High
AGP 3.0: Strap Sampled Low
Voltage OR TESTIN# High
Voltage OR TESTIN# High
hold time is 2 clocks and the maximum hold time is 20 HCLKs.
Normal
Normal
Description
Description
Intel
AGP 3.0: Strap Sampled High
AGP 2.0: Strap Sampled Low
Voltage AND TESTIN# Low
Voltage AND TESTIN# Low
®
82875P MCH Datasheet
XOR Mode
All Z