JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 73

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.5.35
Intel
®
82875P MCH Datasheet
Note: Software must write a 1 to clear bits that are set.
ERRSTS—Error Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register is used to report various error conditions via the SERR HI messaging mechanism. An
SERR HI message is generated on a 0-to-1 transition of any of these flags (if enabled by the
ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is
enabled and generated.
15:10
Bit
9
8
7
6
5
4
3
Intel Reserved
Non-DRAM Lock Error (NDLOCK)—R/WC.
0 = No Lock operation detected.
1 = MCH has detected a lock operation to memory space that did not map into DRAM. This bit is
Software Generated SMI Flag—R/WC.
0 = Source of an SMI was NOT the Device 2 Software SMI Trigger
1 = Source of an SMI was the Device 2 Software SMI Trigger.
Multiple-bit DRAM ECC Error Flag (DMERR)—R/WC.
0 = No non-correctable multiple-bit error for a memory read data transfer.
1 = If this bit is set to 1, a memory read data transfer had a non-correctable multiple-bit error.
Intel Reserved
MCH Detects Unimplemented HI Special Cycle (HIAUSC)—R/WC.
0 = No unimplemented Special Cycle on HI detected.
1 = MCH detects an Unimplemented Special Cycle on HI.
AGP Access Outside of Graphics Aperture Flag (OOGF)—R/WC.
0 = No AGP access to an address that is outside of the graphics aperture range.
1 = AGP access occurred to an address that is outside of the graphics aperture range.
Invalid AGP Access Flag (IAAF)—R/WC.
0 = No invalid AGP access.
1 = AGP access was attempted outside of the graphics aperture and either to the 640 KB – 1 MB
cleared when software writes a 1 to it.
When this bit is set the address, channel number, and device number that caused the error
are logged in the EAP register. Once this bit is set the EAP fields are locked until the
processor clears this bit by writing a 1. Software uses bits [7,0] to detect whether the logged
error address is for Single or Multiple-bit error. Once software completes the error processing,
a value of 1 is written to this bit field to clear the value (back to 0) and unlock the error logging
mechanism.
range or above the top of memory.
C8–C9h
0000h
R/WC
16 bits
Descriptions
Register Description
73