JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 122

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

System Address Map
4.3.2
122
Table 15. Pre-Allocated Memory
Pre-Allocated Memory
Voids of physical addresses that are not accessible as general system memory and reside within the
system memory address range (< TOSM) are created for SMM-mode and legacy VGA graphics
compatibility. For VGA graphics compatibility, pre-allocated memory is only required in non-local
memory configurations. It is the responsibility of BIOS to properly initialize these regions.
Table 15
described in the MCH Control Register Device 0 (GC).
Extended SMRAM Address Range (HSEG and TSEG)
The HSEG and TSEG SMM transaction address spaces reside in this extended memory area.
HSEG
SMM-mode processor accesses to enabled HSEG are remapped to 000A0000h–000BFFFFh. Non-
SMM-mode processor accesses to enabled HSEG are considered invalid are terminated
immediately on the FSB. The exceptions to this rule are Non-SMM-mode Write Back cycles that
are remapped to SMM space to maintain cache coherency. AGP and HI originated cycles to
enabled SMM space are not allowed. Physical DRAM behind the HSEG transaction address is not
remapped and is not accessible.
TSEG
TSEG can be up to 1 MB in size and is the first block after the top of usable physical memory.
SMM-mode processor accesses to enabled TSEG access the physical DRAM at the same address.
Non-SMM-mode processor accesses to enabled TSEG are considered invalid and are terminated
immediately on the FSB. The exceptions to this rule are Non-SMM-mode Write Back cycles that
are directed to the physical SMM space to maintain cache coherency. AGP and HI originated
cycles to enabled SMM space are not allowed.
The size of the SMRAM space is determined by the USMM value in the SMRAM register. When
the extended SMRAM space is enabled, non-SMM processor accesses and all other accesses in this
range are forwarded to the hub interface. When SMM is enabled, the amount of memory available
to the system is equal to the amount of physical DRAM minus the value in the TSEG register.
PCI Memory Address Range (Top of Main Memory to 4 GB)
The address range from the top of main system memory to 4 GB (top of physical memory space
supported by the MCH) is normally mapped via the hub interface to PCI.
As a memory controller hub, there is one exception to this rule.
00000000h–03E7FFFFh
03E80000h–03EFFFFFh
03E80000h–03EFFFFFh
•
Addresses decoded to MMIO for DRAM RCOMP configuration registers.
Memory Segments
details the location and attributes of the regions. Enabling/Disabling these ranges are
R/W
SMM Mode Only - processor
Reads
SMM Mode Only - processor
Reads
Attributes
Available System Memory 62.5 MB
TSEG Address Range
TSEG Pre-allocated Memory
Intel
®
82875P MCH Datasheet
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