JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 71

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.5.34
Intel
®
82875P MCH Datasheet
MCHCFG—MCH Configuration Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
15:13
11:10
Bit
9:6
12
5
4
Number of Stop Grant Cycles (NSG)—R/W. This field represents the number of Stop Grant
transactions expected on the FSB bus before a Stop Grant Acknowledge packet is sent to the
ICH5. This field is programmed by the BIOS after it has enumerated the processors and before it
has enabled Stop Clock generation in the ICH5. Once this field has been set, it should not be
modified. Note that each enabled thread within each processor will generate Stop Grant
Acknowledge transactions.
000 = HI Stop Grant sent after 1 FSB Stop Grant
001 = HI Stop Grant sent after 2 FSB Stop Grants
010–111
Reserved
System Memory Frequency Select (SMFREQ)—RW. The reset value of these bits is 00. The
DDR memory frequency is determined by the following table, and partly determined by the FSB
frequency.
FSBFREQ[1:0] =01
FSBFREQ[1:0] =10
FSBFREQ[1:0] =10
All other combinations are Intel Reserved
Note that Memory I/O Clock always runs at 2X the frequency of the memory clock
NOTE: When writing a new value to this register, software must perform a clock synchronization
Reserved
MDA Present (MDAP)—R/W. This bit works with the VGA Enable bits in the BCTRL1 register of
Device 1 to control the routing of processor-initiated transactions targeting MDA compatible I/O
and memory address ranges. This bit should not be set if Device 1's VGA Enable bit is not set. If
Device 1's VGA enable bit is not set, then accesses to I/O address range x3BCh–x3BFh are
forwarded to HI. If the VGA enable bit is not set, then accesses to I/O address range x3BCh–
x3BFh are treated just like any other I/O accesses. That is, the cycles are forwarded to AGP if the
address is within the corresponding IOBASE and IOLIMIT and ISA enable bit is not set; otherwise,
they are forwarded to HI. MDA resources are defined as the following:
Memory:
I/O:
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to
the hub interface, even if the reference includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGA
0
0
1
1
Reserved
=
sequence to apply the new timings. The new value does not get applied until this is
completed.
C6–C7h
0000h
R/W, RO
16 bits
MDA
0
1
0
1
Reserved
0B0000h–0B7FFFh
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh
(including ISA address aliases, A[15:10] are not used in decode)
Behavior
All references to MDA and VGA go to HI.
Illegal combination (DO NOT USE).
All references to VGA go to Device 1.
MDA-only references (I/O address 3BFh and aliases) will go to HI.
VGA references go to AGP/PCI; MDA references go to HI.
SMFREQ[11:10]=01
SMFREQ[11:10]=01
SMFREQ[11:10]=10
Descriptions
System Memory DDR set to 333 MHz
System Memory DDR set to 333 (320) MHz
System Memory DDR set to 400 MHz
Register Description
71