JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 70

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.5.32
3.5.33
70
LPTT—AGP Low Priority Transaction Timer Register
(Device 0)
Address Offset:
Default Value:
Access:
Size:
LPTT is an 8-bit register similar in function to AMTT. This register is used to control the minimum
tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or
SB mechanisms.
The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in
66-MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does
not necessarily apply to a single transaction but it can span over multiple low-priority transactions
of the same type. After this time expires, the AGP arbiter may grant the bus to another agent if
there is a pending request. The LPTT does not apply in the case of high-priority request where
ownership is transferred directly to high-priority requesting queue. The default value of LPTT is
00h and disables this function. The LPTT value can be programmed with 8-clock granularity. For
example, if the LPTT is programmed to 10h, the selected value corresponds to the time period of
16 AGP (66-MHz) clocks.
TOUD—Top of Used DRAM Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
15:3
Bit
7:3
2:0
Bit
2:0
Low Priority Transaction Timer Count Value (LPTTC)—R/W. The number of clocks
programmed in these bits represents the time slice (measured in eight, 66-MHz clock granularity)
allotted to the current low priority AGP transaction data transfer state).
Reserved
Top of Usable DRAM (TOUD)—R/W. This register contains bits 31:19 of the maximum system
memory address that is usable by the operating system. Address bits 31:19 imply a memory
granularity of 512 KB. Configuration software should set this value to either the maximum amount
of usable memory (minus tseg) in the system or to the minimum address allocated for PCI memory
or the graphics aperture (minus tseg), whichever is smaller. Address bits 18:0 are assumed to be
0000h for the purposes of address comparison.
This register must be set to at least 0400h for a minimum of 64 MB of system memory.
To calculate the value of TOUD, configuration software should set this value to the smaller of the
following tow cases:
NOTE: Even if the OS does not need any PCI space, TOUD should never be programmed above
Reserved
• The maximum amount of usable memory in the system minus optional tseg.
• The address allocated for PCI memory or the graphics aperture minus optional tseg.
FEC0_0000h. If TOUD is programmed above this, address ranges that are reserved will
become accessible to applications.
BDh
10h
RO, R/W
8 bits
C4–C5h
0400h
RO, R/W
16 bits
Descriptions
Descriptions
Intel
®
82875P MCH Datasheet