JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 66

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
66
31:13
12:10
Bit
7:6
2:0
9
8
5
4
3
Reserved
PCAL_Cycle—R/W. Programmed with period for MCH-initiated bus cycle for calibrating I/O
buffers for both master and target. This value is updated with the smaller of the value in
CAL_CYCLE from Master’s and Target’s AGPSTAT.CAL_CYCLE. PCAL_CYCLE is set to 111 by
software only if both Target and Master have AGPSTAT.CAL_CYCLE = 111.
000 = 4 ms
001 = 16 ms
010 = 64 ms (default)
011 = 256 ms
100
111 = Calibration Cycle Not Needed
Side Band Addressing Enable (SBAEN)—R/W. This bit is ignored in AGP 3.0 mode to allow
legacy 2.0 software to work. (When AGP 3.0 is detected, sideband addressing mechanism is
automatically enabled by the hardware.)
0 = Disable.
1 = Enable. Side band addressing mechanism is enabled.
AGP Enable (AGPEN)—R/W.
0 = Disable. MCH ignores all AGP operations, including the sync cycle. Any AGP operations
1 = Enable. MCH responds to AGP operations delivered via PIPE#, or to operations delivered via
Reserved
Greater Than Four Gigabyte Enable (GT4GIGE)—RO. Hardwired to 0 indicating that the MCH,
as an AGP target, does not support addressing greater than 4 GB.
Fast Write Enable (FWEN)—R/W.
0 = Disable. When this bit is cleared, or when the data rate bits are set to 1X mode, the memory
1 = Enable. When this bit is set, the MCH will use the fast write protocol for memory write
Reserved
Data Rate Enable (DRATE)—R/W. The setting of these bits determines the AGP data transfer
rate. One (and only one) bit in this field must be set to indicate the desired data transfer rate. The
same bit must be set on both master and target.
AGP 2.0
001= 1X transfer mode (for AGP 2.0 signaling)
010= 2X transfer mode (NOT SUPPORTED)
100= 4X transfer mode (for AGP 2.0 signaling)
AGP 3.0
001= 4X transfer mode (for AGP 3.0 signaling)
010= 8X transfer mode (for AGP 3.0 signaling)
100= Reserved
–
received while this bit is set to 1 will be serviced, even if this bit is reset to 0. If this bit
transitions from 1 to 0 on a clock edge in the middle of an SBA command being delivered in
1X mode, the command will be issued.
SBA if the AGP Side Band Enable bit is also set to 1.
write transactions from the MCH to the AGP master use standard PCI protocol.
transactions from the MCH to the AGP master. Fast writes will occur at the data transfer rate
selected by the data rate bits (2:0) in this register.
110 = Reserved
Descriptions
Intel
®
82875P MCH Datasheet