JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 84

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.6.11
3.6.12
3.6.13
84
SBUSN1—Secondary Bus Number Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-to-PCI
bridge i.e. to PCI_B/AGP. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI_B/AGP.
SUBUSN1—Subordinate Bus Number Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This register identifies the subordinate bus (if any) that resides at the level below PCI_B/AGP. This
number is programmed by the PCI configuration software to allow mapping of configuration
cycles to PCI_B/AGP.
SMLT1—Secondary Bus Master Latency Timer Register
(Device 1)
Address Offset:
Default Value:
Access:
Size:
This register controls the bus tenure of the MCH on AGP/PCI the same way Device 0 MLT
controls the access to the PCI_A bus.
Bit
7:0
Bit
7:0
Bit
7:3
2:0
Secondary Bus Number (SBUSN)—RO. This field is programmed by configuration software with
the bus number assigned to PCI_B.
Subordinate Bus Number (BUSN)—R/W. This register is programmed by configuration software
with the number of the highest subordinate bus that lies behind the Device 1 bridge. When only a
single PCI device resides on the AGP/PCI_B segment, this register will contain the same value as
the SBUSN1 register.
Secondary MLT Counter Value (MLT)—R/W. Programmable, default = 0 (SMLT disabled)
Reserved
19h
00h
R/W
8 bits
1Ah
00h
R/W
8 bits
1Bh
00h
RO, R/W
8 bits
Descriptions
Descriptions
Descriptions
Intel
®
82875P MCH Datasheet