JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 114

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.9.3
114
DRT—DRAM Timing Register (Device 6, MMR)
Address Offset:
Default Value:
Access:
Size:
This register controls the timing of micro-commands. When in virtual single-channel mode, the
timing fields specified here apply even if two back-to-back cycles are to different physical
channels. That is, the controller acts as if the two cycles are to the same physical channel.
31:11
Bit
9:7
6:5
3:2
1:0
10
4
Intel Reserved
Activate to Precharge delay (t
t
0 = 120 µs
1 = 70 µs
NOTE: DDR333 DRAM requires a shorter T
Activate to Precharge delay (t
t
000 = 10 DRAM clocks
001 = 9 DRAM clocks
010 = 8 DRAM clocks
011 = 7 DRAM clocks
100 = 6 DRAM clocks
101 = 5 DRAM clocks
others = Reserved
CAS# Latency (t
00 = 2.5 DRAM clocks
01 = 2 DRAM clocks
10 = 3 DRAM clocks
11 = Reserved
Intel Reserved
DRAM RAS# to CAS# Delay (t
an active command and a read or write command to that bank.
00 = 4 DRAM clocks
01 = 3 DRAM clocks
10 = 2 DRAM clocks
11 = Reserved
DRAM RAS# Precharge (t
between a precharge command and an active command to the same bank.
00 = 4 DRAM clocks (DDR333)
01 = 3 DRAM clocks
10 = 2 DRAM clocks
11 = Reserved
RAS
RAS
maximum.
minimum.
0060h
00000000h
R/W
32 bits
CL
—
)—R/W.
0063h
RP
)—R/W. This bit controls the number of clocks that are inserted
RAS
RCD
RAS
), Max—R/W. These bits control the number of DRAM clocks for
)—R/W. This bit controls the number of clocks inserted between
), Min—R/W. These bits control the number of DRAM clocks for
Description
RAS
(max) of 70 µs
Intel
®
82875P MCH Datasheet