JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 62

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.5.23
62
SMRAM—System Management RAM Control Register
(Device 0)
Address Offset:
Default Value:
Access:
Size:
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are
treated. The open, close, and lock bits function only when the G_SMRAME bit is set to 1. Also, the
open bit must be reset before the lock bit is set.
Bit
2:0
7
6
5
4
3
Reserved
SMM Space Open (D_OPEN)—R/W. When D_OPEN=1 and D_LCK=0, the SMM space DRAM is
made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM
space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time.
SMM Space Closed (D_CLS)—R/W. When D_CLS = 1, SMM space DRAM is not accessible to
data references, even if SMM decode is active. Code references may still access SMM space
DRAM. This will allow SMM software to reference through SMM space to update the display, even
when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and
D_CLS=1 are not set at the same time. Note that the D_CLS bit only applies to Compatible SMM
space.
SMM Space Locked (D_LCK)—R/W. When D_LCK is set to 1, then D_OPEN is reset to 0 and
D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become read only.
D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full
Reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can
use the D_OPEN function to initialize SMM space and then use D_LCK to “lock down” SMM space
in the future so that no application software (or BIOS itself) can violate the integrity of SMM space,
even if the program has knowledge of the D_OPEN function.
Global SMRAM Enable (G_SMRARE)— R/W/L. If set to 1, then Compatible SMRAM functions
are enabled, providing 128 KB of DRAM accessible at the A0000h address while in SMM (ADS#
with SMM decode). To enable Extended SMRAM function this bit has to be set to 1. Refer to the
section on SMM for more details. Once D_LCK is set, this bit becomes read only.
Compatible SMM Space Base Segment (C_BASE_SEG)—RO. This field indicates the location
of SMM space. SMM DRAM is not remapped. It is simply made visible if the conditions are right to
access SMM space, otherwise the access is forwarded to HI. Since the MCH supports only the
SMM space between A0000h and BFFFFh, this field is hardwired to 010.
9Dh
02h
R/W, RO, Lock
8 bits
Descriptions
Intel
®
82875P MCH Datasheet