JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 40

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.2
40
Platform Configuration Structure
In some previous chipsets, the “MCH” and the “I/O Controller Hub (ICHx)” were physically
connected by PCI bus 0. From a configuration standpoint, both components appeared to be on PCI
bus 0 which was also the system’s primary PCI expansion bus. The MCH contained two PCI
devices while the ICHx was considered one PCI device with multiple functions.
In the 875P chipset platform the configuration structure is significantly different. The MCH and the
ICH5 are physically connected by the hub interface; thus, from a configuration standpoint, the hub
interface is logically PCI bus 0. As a result, all devices internal to the MCH and ICH5 appear to be
on PCI bus 0. The system’s primary PCI expansion bus is physically attached to the ICH5 and,
from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge;
therefore, it has a programmable PCI Bus number. Note that the primary PCI bus is referred to as
PCI_A in this document and is not PCI bus 0 from a configuration standpoint. The AGP appears to
system software to be real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus 0.
The MCH contains four PCI devices within a single physical component. The configuration
registers for the four devices are mapped as devices residing on PCI bus 0.
Reserved
Registers
Default Value
upon a Reset
•
•
•
•
Device 0: Host-HI bridge/DRAM controller. Logically, this appears as a PCI device residing
on PCI bus 0. Physically, Device 0 contains the standard PCI registers, DRAM registers, the
Graphics Aperture controller, configuration for HI, and other MCH specific registers.
Device 1: Host-AGP bridge. Logically this appears as a “virtual” PCI-to-PCI bridge residing
on PCI bus 0. Physically, Device 1 contains the standard PCI-to-PCI bridge registers and the
standard AGP/PCI configuration registers (including the AGP I/O and memory address
mapping).
Device 3: CSA Port. This device appears as a Virtual PCI-CSA (PCI-to-PCI) bridge device.
Device 6: Function 0: Overflow Device. The purpose of this device is to provide additional
configuration register space for Device 0.
Term
In addition to reserved bits within a register, the MCH contains address locations in the
configuration space of the Host-HI bridge entity that are marked either “Reserved” or
“Intel Reserved”. The MCH responds to accesses to “Reserved” address locations by
completing the host cycle. When a “Reserved” register location is read, a zero value is
returned. (“Reserved” registers can be 8, 16, or 32 bits in size). Writes to “Reserved”
registers have no effect on the MCH. Registers that are marked as “Intel Reserved” must
not be modified by system software. Writes to “Intel Reserved” registers may cause
system failure. Reads to “Intel Reserved” registers may return a non-zero value.
Upon a reset, the MCH sets all of its internal configuration registers to predetermined
default states. Some register values at reset are determined by external strapping
options. The default state represents the minimum functionality feature set required to
successfully bring up the system. Hence, it does not represent the optimal system
configuration. It is the responsibility of the system initialization software (usually BIOS) to
properly determine the DRAM configurations, operating parameters and optional system
features that are applicable, and to program the MCH registers accordingly.
Description
Intel
®
82875P MCH Datasheet