JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 64

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.5.25
3.5.26
64
ACAPID—AGP Capability Identifier Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register provides standard identifier for AGP capability.
AGPSTAT—AGP Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register reports AGP device capability/status.
31:24
23:20
19:16
31:24
23:16
15:13
12:10
15:8
Bit
7:0
Bit
8:6
9
5
Reserved
Major AGP Revision Number (MAJREV)—RO. These bits provide a major revision number of
AGP specification to which this version of MCH conforms. This field is hardwired to value of 0011b
(i.e., implying Rev 3.x).
Minor AGP Revision Number (MINREV)—RO. These bits provide a minor revision number of
AGP specification to which this version of MCH conforms. This number is hardwired to a value of
0000 which implies that the revision is x.0. Together with major revision number this field identifies
the MCH as an AGP REV 3.0 compliant device.
Next Capability Pointer (NCAPTR)—RO. AGP capability is the first and the last capability
described via the capability pointer mechanism and therefore these bits are hardwired to 00h to
indicate the end of the capability linked list.
AGP Capability ID (CAPID)—RO. This field identifies the linked list item as containing AGP
registers. This field has a value of 0000_0010b assigned by the PCI SIG.
Request Queue (RQ)—RO. Hardwired to 1Fh to indicate a maximum of 32 outstanding AGP
command requests can be handled by the MCH. This field contains the maximum number of AGP
command requests the MCH is configured to manage.
Reserved
ARQSZ—RO. LOG2 of the optimum asynchronous request size in bytes minus 4 to be used with
the target. The Master should attempt to issue a group of sequential back-to-back asynchronous
requests that total to this size and for which the group is naturally aligned.
Optimum_request_size = 2 ^ (ARQSZ+4).
Hardwired to 010 to indicate 64 B.
CAL_Cycle—RO. This field specifies the required period for MCH-initiated bus cycle for calibrating
I/O buffers.
Hardwired to 010 to indicate 64 ms.
Side Band Addressing Support (SBA)—RO. Hardwired to 1 indicating that the MCH supports
side band addressing.
Reserved
Greater Than Four Gigabyte Support (GT4GIG)—RO. Hardwired to 0 indicating that the MCH
does not support addresses greater than 4 GB.
A0h–A3h
00300002h
RO
32 bits
A4–A7h
1F000217h in AGP 2.0; 1F004A13h in AGP 3.0 mode
RO
32 bits
Descriptions
Descriptions
Intel
®
82875P MCH Datasheet