JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 65

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.5.27
Intel
®
82875P MCH Datasheet
AGPCMD—AGP Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register provides control of the AGP operational parameters.
2:0
Bit
4
3
Fast Write Support (FW)—RO. Hardwired to 1 indicating that the MCH supports fast writes from
the processor to the AGP master.
AGP 3.0 mode (AGP 30_MOD)—RO. This bit is set by the hardware on the assertion of PWROK
based on the AGP 3.0 detection via the Vref comparator on the GVREF pin. In AGP 2.0 mode,
GVREF is driven to 0.75 V, while in AGP 3.0 mode, GVREF is driven to 0.35 V. Note that the output
of the Vref comparator is used “live” prior to the assertion of PWROK and used to select the
appropriate pull-up, pull-down, or termination on the I/O buffer depending on the mode selected.
0 = AGP 2.0 (1.5 V signaling) mode.
1 = AGP 3.0 signaling mode.
Data Rate Support (RATE)—RO. After reset, the MCH reports its data transfer rate capability.
AGP 2.0 Mode
AGP 3.0 Mode
NOTES:
1. In AGP 3.0 mode (AGP_MODE=1) these bits are 011 indicating that both 4X and 8X modes are
2. In AGP 2.0 mode these bits are 111 indicating that 4X, 2X, and 1X modes are supported;
• Bit 0 identifies if AGP device supports 1X data transfer mode
• Bit 1 identifies if AGP device supports 2X data transfer mode (unsupported)
• Bit 2 identifies if AGP device supports 4X data transfer
• Bit 0 identifies if AGP device supports 4X data transfer mode
• Bit 1 identifies if AGP device supports 8X data transfer mode
• Bit 2 is reserved
supported.
however, in the 82875P MCH 2X is not supported.
A8–ABh
00000000h in AGP 2.0 mode
00000A00h in AGP 3.0 mode
RO, R/W
32 bits
Descriptions
Register Description
65