JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 29

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

2.5
2.5.1
Intel
®
82875P MCH Datasheet
AGP Interface Signals
AGP Addressing Signals
NOTES:
1. The previous table contains two mechanisms to queue requests by the AGP master. Note that the master can
2. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing).
3. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
GPIPE# (2.0)
DBI_HI (3.0)
GSBA[7:0] (2.0)
GSBA#[7:0] (3.0)
Signal Name
only use one mechanism. When GPIPE# is used to queue addresses the master is not allowed to queue
addresses using the SB bus. For example, during configuration time, if the master indicates that it can use
either mechanism, the configuration software will indicate which mechanism the master will use. Once this
choice has been made, the master will continue to use the mechanism selected until the master is reset (and
reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static
decision when the device is first being configured after reset.
Type
AGP
AGP
I/O
I
Pipelined Read: This signal is asserted by the current master to indicate a full
width address is to be queued by the target. The master enqueues one request
each rising clock edge while GPIPE# is asserted. When GPIPE# is deasserted
no new requests are enqueued across the GAD bus.
GPIPE# may be used in AGP 2.0 signaling modes, but is not permitted by the
AGP 3.0 Spec. When operating in AGP 3.0 signaling mode, the GPIPE# signal
is used for DBI_HI.
GPIPE# is a sustained tri-state signal from the master (graphics controller) and
is an input to the MCH.
In AGP 3.0 signaling mode this signal is Dynamic Bus Inversion HI:
DYNAMIC BUS Inversion HI: This signal goes along with GAD[31:16] to
indicate whether GAD[31:16] must be inverted on the receiving end.
The GADSTBF1 and GADSTBS1 strobes are used with DBI_HI. In AGP 3.0
4X data rate mode dynamic bus inversion is disabled by the MCH while
transmitting (data never inverted and BI_HI driven low); dynamic bus inversion
is enabled when receiving data. For 8X data rate, dynamic bus inversion is
enabled when transmitting and receiving data.
Sideband Address: This bus provides an additional bus to pass address and
command to the MCH from the AGP master.
NOTE: In AGP 2.0 signaling mode, when sideband addressing is disabled,
• DBI_HI = 0: GAD[31:16] are not inverted so receiver may use as is.
• DBI_HI= 1: GAD[31:16] are inverted so receiver must invert before use.
these signals are isolated. When sideband addressing is enabled,
internal pull-ups are enabled to prevent indeterminate values on them
in cases where the graphics card may not have its GSBA[7:0] output
drivers enabled yet.
Description
Signal Description
29