JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 87

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.6.17
Intel
®
82875P MCH Datasheet
MBASE1—Memory Base Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This register controls the processor-to-PCI_B non-prefetchable memory access routing based on
the following formula:
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom four bits of this register are read only and return 0’s
when read. This register must be initialized by the configuration software. For the purpose of
address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1-MB boundary.
15:4
3:0
Bit
Memory Address Base (MBASE)—R/W. This field corresponds to A[31:20] of the lower limit of
the memory range that will be passed by the Device 1 bridge to AGP/PCI_B.
Reserved
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
20–21h
FFF0h
RO, R/W
16 bits
Descriptions
Register Description
87