JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 107

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.8.2
3.8.3
Intel
®
82875P MCH Datasheet
DID6—Device Identification Register (Device 6)
Address Offset:
Default Value:
Access:
Size:
This 16-bit register, combined with the Vendor Identification register, uniquely identifies any PCI
device.
PCICMD6—PCI Command Register (Device 6)
Address Offset:
Default Value:
Access:
Size:
Since MCH Device 0 does not physically reside on PCI_A, many of the bits are not implemented.
15:10
15:0
Bit
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back-to-Back Enable (FB2B)—RO. Hardwired to 0.
SERR Enable (SERRE)—RO. Hardwired to 0.
Address/Data Stepping Enable (ADSTEP)—RO. Hardwired to 0.
Parity Error Enable (PERRE)—RO. Hardwired to 0.
VGA Palette Snoop Enable (VGASNOOP)—RO. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0.
Special Cycle Enable (SCE)—RO. Hardwired to 0.
Bus Master Enable (BME)—RO. Hardwired to 0.
Memory Access Enable (MAE)—R/W. Set this bit to 1 to enable Device 6 memory space
accesses.
0 = Disable (default).
1 = Enable.
I/O Access Enable (IOAE)—R/W. This bit must be set to 1 to enable the I/O address range
defined in the IOBASE3 and IOLIMIT3 registers.
0 = Disable (default).
1 = Enable.
Device Identification Number (DID)—RO. This is a 16-bit value assigned to the MCH Host-HI
bridge Function 0.
02–03h
257Eh
RO
16 bits
04–05h
0000h
RO, R/W
16 bits
Descriptions
Descriptions
Register Description
107