JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 80

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.6.3
80
PCICMD1—PCI Command Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back-to-Back Enable (FB2B)—RO. Hardwired to 0.
SERR Message Enable (SERRE)—R/W. This bit is a global enable bit for Device 1 SERR
messaging. The MCH communicates the SERR# condition by sending a SERR message to the
Intel
0 = Disable. SERR message is not generated by the MCH for Device 1.
1 = Enable. MCH is enabled to generate SERR messages over HI for specific Device 1 error
Address/Data Stepping (ADSTEP)—RO. Hardwired to 0.
Parity Error Enable (PERRE)—RO. Hardwired to 0. Parity checking is not supported on the
primary side of this device.
Reserved
Memory Write and Invalidate Enable (MWIE)—RO. This bit is implemented as read only and
returns a value of 0 when read.
Special Cycle Enable (SCE)—RO. Hardwired to 0.
Bus Master Enable (BME)—R/W.
0 = Disable. AGP Master initiated Frame# cycles will be ignored by the MCH. The result is a
1 = Enable. AGP master initiated Frame# cycles will be accepted by the MCH if they hit a valid
Memory Access Enable (MAE)—R/W.
0 = Disable. All of Device 1’s memory space is disabled.
1 = Enable. Enables the Memory and Pre-fetchable memory address ranges defined in the
IO Access Enable (IOAE)—R/W.
0 = Disable. All of Device 1’s I/O space is disabled.
1 = Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and
®
conditions that are individually enabled in the BCTRL1 register. The error status is reported in
the PCISTS1 register.
master abort. Ignoring incoming cycles on the secondary side of the PCI-to-PCI bridge
effectively disabled the bus master on the primary side. (default)
address decode range. This bit has no effect on AGP Master originated SBA or PIPE# cycles.
MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
IOLIMIT1 registers.
ICH5.
04–05h
0000h
RO, R/W
16 bits
Descriptions
Intel
®
82875P MCH Datasheet