JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 33

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

2.5.5.1
2.6
Intel
®
82875P MCH Datasheet
PCI Pins During PCI Transactions on AGP Interface
NOTES:
PCI signals described above behave according to PCI 2.1 specifications when used to perform PCI
transactions on the AGP interface.
Clocks, Reset, and Miscellaneous
1. PCIRST# from the ICH5 is connected to RSTIN# and is used to reset AGP interface logic within the MCH.
2. LOCK# signal is not supported on the AGP interface (even for PCI operations).
3. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing).
4. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
DBI_LO (3.0 only)
TESTP[3:0]
TESTP[29:4]
HCLKP
HCLKN
GCLKIN
RSTIN#
PWROK
EXTTS#
Signal Name
The AGP agent will also typically use PCIRST# provided by the ICH5 as an input to reset its internal logic.
Signal Name
SSTL_2
CMOS
LVTTL
(3.3 V)
LVTTL
(3.3 V)
LVTTL
(3.3 V)
LVTTL
(3.3 V)
GPIO
Type
3.3 V
O
O
I
I
I
I
I
Type
AGP
I/O
Test Point: These signals are used as part the XOR/ALL Z test chain and should
be routed to a VIA for XOR testing.
Test Point: These signals route to pull-up for XOR/ALL Z test chain usage.
Differential Host Clock In: These pins receive a low-voltage differential host
clock from the external clock synthesizer. This clock is used by all of the MCH
logic that is in the Host clock domain. 0.7 V
66 MHz Clock In:. This pin receives a 66 MHz clock from the clock synthesizer.
This clock is used by AGP/PCI and HI clock domains. Note that this clock input is
required to be 3.3 V tolerant.
Reset In: When asserted, this signal asynchronously resets the MCH logic. This
signal is connected to the PCIRST# output of the ICH5. All AGP/PCI output and
bi-directional signals will also tri-state compliant to PCI Revision 2.0 and 2.1
specifications. This input should have a Schmitt trigger to avoid spurious resets.
Note that this input needs to be 3.3 V tolerant.
Power OK: When asserted, PWROK is an indication to the MCH that the core
power and GCLKIN have been stable for at least 10 µs.
External Thermal Sensor Input: EXTTS# is an open-drain signal indicating an
Over-Temp condition in the platform. This signal should remains asserted for as
long as the Over-temp Condition exists. This input pin can be programmed to
activate hardware management of memory reads and writes and/or trigger
software interrupts.
Dynamic Bus Inversion LO: This signal goes along with GAD[15:0] to
indicate whether GAD[15:0] must be inverted on the receiving end.
The GADSTBF1 and GADSTBS1 strobes are used with the DBI_LO. Dynamic
bus inversion is used in AGP 3.0 signaling mode only. In AGP 3.0 4X data rate
mode dynamic bus inversion is disabled by the MCH while transmitting (data
never inverted and DBI_LO driven low); it is enabled when receiving data, For
8X data rate, dynamic bus inversion is enable when transmitting and receiving
data.
• DBI_LO= 0: GAD[15:0] are not inverted so receiver may use as is.
• DBI_LO= 1: GAD[15:0] are inverted so receiver must invert before use.
Description
Description
Signal Description
33