JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 91

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.6.22
Intel
®
82875P MCH Datasheet
ERRCMD1—Error Command Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
7:1
Bit
0
Reserved
SERR on Receiving Target Abort (SERTA)—R/W.
0 = The MCH does not assert an SERR message upon receipt of a target abort on PCI_B. SERR
1 = The MCH generates an SERR message over HI upon receiving a target abort on PCI_B.
messaging for Device 1 is globally enabled in the PCICMD1 register.
40h
00h
RO, R/W
8 bits
Descriptions
Register Description
91