JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 117

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

System Address Map
4.1
Intel
®
82875P MCH Datasheet
Note: All of these ranges must be unique and non-overlapping. There are no hardware interlocks to
The processor in an 875P chipset system supports 4 GB of addressable memory space and
64 KB+3 of addressable I/O space. There is a programmable memory address space under the
1-MB region that is divided into regions that can be individually controlled with programmable
attributes (e.g., disable, read/write, write only, or read only). Attribute programming is described in
the
separate memory regions.
The Pentium 4 processor family supports addressing of memory ranges larger than 4 GB. The
MCH claims any processor access over 4 GB and terminates the transaction without forwarding it
to the hub interface or AGP (discarding the data terminates writes). For reads, the MCH returns all
0’s on the host bus. Note that the 875P chipset platform does not support the PCI Dual Address
Cycle Mechanism and, therefore, does not allow addressing of greater than 4 GB on either the hub
interface or AGP interface.
In the following sections, it is assumed that all of the compatibility memory ranges reside on the
hub interface/PCI. The exception to this rule is VGA ranges that may be mapped to AGP. In the
absence of more specific references, cycle descriptions referencing PCI should be interpreted as the
Hub Interface/PCI, while cycle descriptions referencing AGP are related to the AGP bus.
The 875P chipset memory map includes a number of programmable ranges
prevent problems in the case of overlapping ranges. Accesses to overlapped ranges may produce
indeterminate results.
System Memory Address Ranges
The MCH provides a maximum system memory address decode space of 4 GB. The MCH does not
remap APIC memory space. The MCH does not limit system memory space in hardware. It is the
BIOS or system designers responsibility to limit memory population so that adequate PCI,
AGP, High BIOS, and APIC memory space can be allocated.
system memory address map.
regions as defined and supported by the MCH.
Chapter
3. This section focuses on how the memory space is partitioned and the use of the
Figure 10
provides additional details on mapping specific memory
Figure 9
System Address Map
provides a simplified
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