JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 96

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.7.6
3.7.7
3.7.8
96
SUBC3—Class Code Register (Device 3)
Address Offset:
Default Value:
Access:
Size:
This register contains the Sub-Class Code for the MCH device 3.
BCC3—Base Class Code Register (Device 3)
Address Offset:
Default Value:
Access:
Size:
This register contains the Base Class Code of the MCH Device 3.
MLT3—Master Latency Timer Register (Device 3)
Address Offset:
Default Value:
Access:
Size:
This functionality is not applicable. It is described here since these bits should be implemented as a
read/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.”
7:0
7:0
7:3
2:0
Bit
Bit
Bit
Sub-Class Code (SUBC)—RO. This is an 8-bit value that indicates the category of bridge into
which the Device 3 of the MCH falls.
04h = PCI-to-PCI bridge.
Base Class Code (BASEC)—RO. This is an 8-bit value that indicates the Base Class Code for the
MCH Device 3.
06h = Bridge device.
Scratchpad MLT (NA7:3)—R/W. These bits return the value with which they are written; however,
they have no internal function and are implemented as a scratchpad merely to avoid confusing
software.
Reserved
0Ah
04h
RO
8 bits
0Bh
06h
RO
8 bits
0Dh
00h
RO, RW
8 bits
Description
Description
Description
Intel
®
82875P MCH Datasheet