JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 115

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.9.4
Intel
®
82875P MCH Datasheet
DRC—DRAM Controller Mode Register (Device 6, MMR)
Address Offset:
Default Value:
Access:
Size:
31:30
27:23
22:21
19:18
17:11
10:8
Bit
29
28
20
7
Reserved
Initialization Complete (IC)—R/W. This bit is used for communication of the software state
between the memory controller and the BIOS.
1 = BIOS sets this bit to 1 after initialization of the DRAM memory array is complete.
Reserved
Intel Reserved
Number of Channels (CHAN)—RO. This field reflects that the MCH controller supports two
modes of operation.
00 = Single-channel or virtual single-channel
01 = Dual-channel
10 = Reserved
11 = Reserved
Reserved
DRAM Data Integrity Mode (DDIM)—R/W. These bits select data integrity mode.
00 = Non-ECC mode
01 = ECC enabled
Other = Reserved
Reserved
Refresh Mode Select (RMS)—R/W. This field determines whether refresh is enabled and, if so, at
what rate refreshes will be executed.
000 = Reserved
001 = Refresh enabled. Refresh interval is 15.6 µsec
010 = Refresh enabled. Refresh interval is 7.8 µsec
011 = Refresh enabled. Refresh interval is 64 µsec
111 = Refresh enabled. Refresh interval is 64 clocks (fast refresh mode)
Other = Reserved
Reserved
0068h
00000001h
R/W, RO
32 bits
—
006Bh
Description
Register Description
115