JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 59

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.5.21
Intel
®
82875P MCH Datasheet
PAM[0:6]—Programmable Attribute Map Registers
(Device 0)
Address Offset:
Default Value:
Attribute:
Size:
The MCH allows programmable memory attributes on 13 Legacy memory segments of various
sizes in the 768-KB to 1-MB address range. Seven Programmable Attribute Map (PAM) Registers
are used to support these features. Cacheability of these areas is controlled via the MTRR registers
in the processor. Two bits are used to specify memory attributes for each memory segment. These
bits apply to host initiator only access to the PAM areas. MCH will forward to main memory for
any AGP, PCI, or HI initiated accesses to the PAM areas. These attributes are:
RE
WE
The RE and WE attributes permit a memory segment to be read only, write only, read/write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is read only.
Each PAM register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit
field. The four bits that control each region have the same encoding defined in the following table.
At the time that a HI or AGP access to the PAM region occurs, the targeted PAM segment must be
programmed to be both readable and writable.
Reserved
Bits [7, 3]
X
X
X
X
Read Enable. When RE = 1, the host read accesses to the corresponding memory segment
are claimed by the MCH and directed to main memory. Conversely, when RE = 0, the host
read accesses are directed to PCI_A.
Write Enable. When WE = 1, the host write accesses to the corresponding memory
segment are claimed by the MCH and directed to main memory. Conversely, when
WE = 0, the host write accesses are directed to PCI_A.
Bits [6, 2]
Reserved
X
X
X
X
90
00h
R/W, RO
8 bits
–
96h (PAM0–PAM6)
Bits [5, 1]
WE
0
0
1
1
Bits [4, 0]
RE
0
1
0
1
Disabled DRAM is disabled and all accesses are directed to
the hub interface. The MCH does not respond as a PCI
target for any read or write access to this area.
Read Only. Reads are forwarded to DRAM and writes are
forwarded to the hub interface for termination. This write
protects the corresponding memory segment. The MCH will
respond as an AGP or the hub interface target for read
accesses but not for any write accesses.
Write Only. Writes are forwarded to DRAM and reads are
forwarded to the hub interface for termination. The MCH will
respond as an AGP or hub interface target for write
accesses but not for any read accesses.
Read/Write. This is the normal operating mode of main
memory. Both read and write cycles from the host are
claimed by the MCH and forwarded to DRAM. The MCH will
respond as an AGP or hub interface target for both read
and write accesses.
Description
Register Description
59