JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 111

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.9
3.9.1
Intel
Table 13. Device 6 Memory-Mapped I/O Register Address Map
®
82875P MCH Datasheet
Note: All accesses to these memory-mapped registers must be made as a single DWord (4 bytes) or less.
Device 6 Memory-Mapped I/O Register Space
The DRAM timing and delay registers are located in the memory-mapped register (MMR) space of
Device 6.
Access must be aligned on a natural boundary.
DRB[0:7]—DRAM Row Boundary Registers (Device 6, MMR)
Address Offset:
Default Value:
Access:
Size:
The DRAM row Boundary registers define the upper boundary address of each DRAM row. Each
row has its own single-byte DRB register. The granularity of these registers is 64 MB. For
example, a value of 1 in DRB0 indicates that 64 MB of DRAM has been populated in the first row.
When in either of the two dual-channel modes, the granularity of these registers is still 64 MB. In
this case, the lowest order bit in each register is always programmed to 0 yielding a minimum
granularity of 128 MB. Bit 7 of each of these registers is reserved and must be programmed to 0.
The remaining 7 bits of each of these registers are compared against address lines 31:26 to
determine which row is being addressed by the current cycle. In either of the dual-channel modes,
the MCH supports a total of 4 rows of memory (only DRB0-3 are used). When in either of the dual-
006C
0008
0068
0014
0060
0064
Address
Offset
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0010h
0012h
0013h
0011h
–
–
–
–
–
–
000Bh
005Fh
0063h
0067h
006Bh
FFFFh
Table 13
Register
Symbol
DRA0,1
DRA2,3
DRA4,5
DRA6,7
DRB0
DRB1
DRB2
DRB3
DRB4
DRB5
DRB6
DRB7
provides the register address map for this set of registers.
DRC
DRT
0000h–0007h (DRB0–DRB7)
00h
RO, R/W
8 bits each register
—
—
—
—
DRAM Row 0 Boundary
DRAM Row 1 Boundary
DRAM Row 2 Boundary
DRAM Row 3 Boundary
DRAM Row 4 Boundary
DRAM Row 5 Boundary
DRAM Row 6 Boundary
DRAM Row 7 Boundary
Intel Reserved
DRAM Row 0,1 Attribute
DRAM Row 2,3 Attribute
DRAM Row 4,5 Attribute
DRAM Row 6,7 Attribute
Intel Reserved
DRAM Timing
Intel Reserved
DRAM Controller Mode
Intel Reserved
Register Name
Default Value
0000 0000h
0001 0001h
Register Description
01h
01h
01h
01h
01h
01h
01h
01h
00h
00h
00h
00h
—
—
—
—
RO, RW
RO, RW
RO, RW
RO, RW
RO, RW
RO, RW
RO, RW
RO, RW
RO, RW
RO, RW
RO, RW
RO, RW
RW, RO
Access
RW
—
—
—
—
111