JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 50

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.5.4
50
PCISTS—PCI Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI
interface. Since MCH Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
10:9
Bit
6:5
3:0
15
14
13
12
11
8
7
4
Detected Parity Error (DPE)—RO. Hardwired to 0. Writes to this bit position have no effect.
Signaled System Error (SSE)—R/WC.
0 = Software sets this bit to 0 by writing a 1 to this bit.
1 = MCH Device 0 generated an SERR message over HI for any enabled Device 0 error
Received Master Abort Status (RMAS)—R/WC.
0 = Software sets this bit to 0 by writing a 1 to this bit.
1 = MCH generated a HI request that receives a Master Abort completion packet or Master Abort
Received Target Abort Status (RTAS)—R/WC.
0 = Software sets this bit to 0 by writing a 1 to this bit.
1 = MCH generated a HI request that receives a Target Abort completion packet or Target Abort
Signaled Target Abort Status (STAS)—RO. Hardwired to 0. The MCH will not generate a Target
Abort HI completion packet or Special Cycle.
DEVSEL Timing (DEVT)—RO. Hardwired to 00. Device 0 does not physically connect to PCI_A.
These bits are set to 00 (fast decode) so that optimum DEVSEL timing for PCI_A is not limited by
the MCH.
Master Data Parity Error Detected (DPD)—RO. Hardwired to 0. PERR signaling and messaging
are not implemented by the MCH.
Fast Back-to-Back (FB2B)—RO. Hardwired to 1. Device 0 does not physically connect to PCI_A.
This bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for PCI_A is
not limited by the MCH.
Reserved
Capability List (CLIST)—RO. Hardwired to 1 to indicate to the configuration software that this
device/function implements a list of new capabilities. A list of new capabilities is accessed via
register CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset
pointing to the start address within configuration space of this device where the AGP capability
standard register resides.
Reserved
condition. Device 0 error conditions are enabled in the PCICMD and ERRCMD registers.
Device 0 error flags are read/reset from the PCISTS or ERRSTS registers.
Special Cycle.
Special Cycle.
06–07h
0090h
RO, R/WC
16 bits
Descriptions
Intel
®
82875P MCH Datasheet