JG82875 S L8DB Intel, JG82875 S L8DB Datasheet - Page 104

• Manufacturer Part Number: JG82875 S L8DB
• Manufacturer: Intel

Specifications of JG82875 S L8DB

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.7.20
104
Table 11. VGAEN and MDAP Definitions
BCTRL3—Bridge Control Register (Device 3)
Address Offset:
Default Value:
Access:
Size:
VGAEN
Bit
7
6
5
4
3
2
1
0
0
0
1
1
Fast Back-to-Back Enable (FB2BEN)—RO. Hardwired to 0. The MCH does not generate fast
back-to-back cycles as a master on AGP.
Secondary Bus reset (SREST)—RO. Hardwired to 0. The MCH does not support the generation of
reset via this bit on the AGP.
Master Abort Mode (MAMODE)—RO. Hardwired to 0. This means that, when acting as a master
on CSA, the MCH will discard writes and return all 1’s during reads when a master abort occurs.
Reserved
VGA Enable (VGAEN)—R/W. This bit controls the routing of processor-initiated transactions
targeting VGA compatible I/O and memory address ranges. This bit works in conjunction with the
MCHCFG[MDAP] bit (Device 0, offset C6h) as described in
ISA Enable (ISAEN)—R/W. This bit modifies the response by the MCH to an I/O access issued by
the processor that targets ISA I/O addresses. This applies only to I/O addresses that are enabled by
the IOBASE and IOLIMIT registers.
0 = Disable (default). All addresses defined by the IOBASE and IOLIMIT for processor I/O
1 = Enable. The MCH will not forward to CSA any I/O transactions addressing the last 768 bytes in
SERR Enable (SERREN)—RO. Hardwired to 0. This bit normally controls forwarding SERR# on the
secondary interface to the primary interface. The MCH does not support the SERR# signal on the
CSA bus.
Parity Error Response Enable (PEREN)—RO. Hardwired to 0
transactions will be mapped to CSA.
each 1-KB block, even if the addresses are within the range defined by the IOBASE and
IOLIMIT registers. Instead of going to CSA, these cycles will be forwarded to the hub interface
where they can be subtractively or positively claimed by the ISA bridge.
MDAP
3Eh
00h
R/W, RO
8 bits
0
1
0
1
All References to MDA and VGA space are routed to HI.
Illegal combination.
All VGA references are routed to this bus. MDA references are routed to HI.
All VGA references are routed to this bus. MDA references are routed to HI.
Description
Description
Table
Intel
11.
®
82875P MCH Datasheet