ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 101

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
1.6: PCINT Base Address 2 (Mem for Register)
This register specifies the base address of where in PCI memory space the IBM3206K0424 registers will be
mapped. When written with ’1’s and read back, the least significant bits read back as ’0’ will indicate the
amount of memory space required for this device to operate. For example, when a value of ’FFFFFFFF’ is
written, a value read of ’FFFFFF00’ indicates that 256 bytes of address space this required. See bit defini-
tions.
The programming of this bit depends on whether the IBM3206K0424 is in 64-bit addressing mode or not.
When in 64-bit addressing mode, bit 4 of the PCINT 64 bit Controller Register is set to ’1’, and this register
specifies a memory address. When the the IBM3206K0424 is not in 64-bit addressing mode because bit 4 of
the PCINT 64-bit Control Register is set to ‘0’, this register specifies an I/O address. See bit definitions and
PCINT 64-bit Control Register on page 116.
Length
Type
Address
Restrictions
Power on Reset value
(Big Endian)
Power on Reset value
(Little Endian)
When in 64-bit Addressing Mode (that is, bit 64 of PCINT 64-bit Control Register is set to ’1’):
pnr25.chapt04.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Bit(s)
31-0
PCI Spec
31-0
Upper part of Base Address
32 bits
Read/Write
XXXX 0014
Can be written or read during configuration cycle, memory cycle when enabled (see
PCINT Base Address Control Register on page 111), or an I/O cycle. This register
is documented as big endian, but how data is presented on the PCI bus depends
on how the controls are set in the PCINT Endian Control Register. Bit 16 in the
PCINT Base Address Control Register must be set to allow the IBM3206K0424 to
decode addresses for this range.
X’00000000’
X’00000000’
Name
Base Address
This register is used to hold the upper 32 bits of address during a 64 bit
addressing dual cycle access.
The IOP Bus Specific Interface Controller (PCINT)
IBM Processor for Network Resources
Description
8
7
6
5
4
Page 101 of 676
IBM3206K0424
3
2
1
0