ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 285

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
10.11: ABR Timer Prescaler Register
This register determines the length of time for a tick of the RM Cell Timer. This controls the rate that the cell
scheduling counters are incremented. Each clock cycle, the value in this register is added to a 24-bit counter.
When the upper bit of the counter changes state, the RM Cell Timer is incremented. This should be set to
value of 0.78 ms. It will be initialized to 0.78 ms assuming a 30-ns clock (as set up in SCLOCK). The following
formula should be used to determine the value to load in this register:
Length
Type
Address
Power On Value
Restrictions
10.12: RM Cell Timer
This register is used to keep track of the last time that an ABR RM cell was sent. Its period should be 0.78 ms.
Length
Type
Address
Power On Value
Restrictions
pnr25.chapt05.01
August 14, 2000
23 22 21 20 19 18 17 16 15 14 13 12 11 10
23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit(s)
Bit(s)
23-0
23-0
This value will determine the rate at which the ABR counter is advanced.
Timer value.
ABR Timer Prescaler = (clock interval/0.78 ms) x 2∗∗23.
24 bits
Read/Write
XXXX 127C
X’0000A2’
This register should be written only at initialization time.
24 bits
Read/Write
XXXX 126C
X’000000’
None
ABR Counter Rate
RM Timer Value
9
9
8
8
7
7
Description
Description
6
6
5
5
4
4
3
3
IBM Processor for Network Resources
2
2
1
1
0
0
Transmit Buffer (CSKED)
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IBM3206K0424