ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 405

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
pnr25.chapt05.01
August 14, 2000
25-21
23-20
19-16
Bit(s)
10-4
26
15
14
13
12
11
3
2
1
0
Always Transfer cell
Reserved
Transmit PHY WatchDog Timer
Receive PHY WatchDog Timer
Enable Transmit Side WatchDog
Timer
Enable Receive Side WatchDog
Timer
Disable PHY Bus Drivers
Reserved
SERDES External Loopback
Mode
Utopia Cell Length
Override Standard Utopia Cell
Length
Loop back mode
Enable Transmit Multi-Drop
Enable Receive Multi-Drop
Name
When this bit is set to ’1’, the TCA (transmit cell available) will be ignored until the cur-
rent transfer ends. This mode is recommended when talking to a single drop Utopia
device. The default for this bit is ’0’.
Reserved
These four bits are the cycles the transmit side (LINKT) will wait before switching to
another PHY. If the timer times out, a status bit in LINKC Interrupt/Status Register will
be set for the offending PHY.
These four bits are the cycles the receive side (LINKR) will wait before switching to
another PHY. If the timer times out, a status bit in LINKC Interrupt/Status Register will
be set for the offending PHY.
This bit, when set to ’1’, causes LINKT to timeout if the PHY has started to take data
but is now unable to take data for the number of cycles determined by the Transmit
PHY Watchdog Timer (bits 23-20). The Timer is only valid if the transmit side is in
multi-drop mode.
This bit, when set to ’1’, causes LINKR to timeout if the PHY is receiving data and is
unable to provide data for the number of cycles determined by the Receive PHY
watchdog timer (bits 19-16). The timer is only valid if the receive side of LINKC is in
multi-drop mode and the PHY is a Utopia device.
This bit, when set to ’1’, tri-states the drivers of the PHY bus. When set to ’0’, the driv-
ers are enabled.
Reserved
When this bit is set, the Receive Side SERDES input will be routed to the Transmit
Side SERDES output.
These seven bits will define what the Utopia cell length (in bytes) will be if the override
standard utopia cell length bit (bit 3) is set to ’1’. The upper limit of this register is 64
and the lower limit is one. The default value of these bits is x'0110100'.
When this bit is set to ’1’, the standard utopia cell length (52 or 53 bytes) will be
replaced by the value in bits 10-4. This bit will have no affect on PHYs that aren't Uto-
pia and it will disable the HEC generation for any Utopia PHY.
This bit set to ’1’ places the IBM3206K0424 in an internal loop back mode. The PHY
interface will be disabled. The clocks to LINKT and LINKR should be set to the same
source in the Clock Control Register. This bit is flushed to a ’1’ after POR. For loop-
back to work in multi-drop mode the transmit and receive configurations must be the
same. When a configuration is set up for Utopia Cell-based transmission the receive
and transmit sides should be identical in all ways. These include odd/even parity, data
path length, 52-byte cell mode, null cell generation, and HEC generation of null cells.
The additional header bytes should be set to '00' when in loopback mode. Please see
the tableLegal Loopback Configurations on page 406.
Setting this bit will put the transmit side into multi-drop mode. In multi-drop mode the
IBM3206K0424 will support four configurations and four unique ports. This bit should
not be set if the transmit side is connected to the Internal SONET Framer. Configura-
tion 0 Transmit Control Register will control the transmit interface. If this bit is not set,
the IBM3206K0424 is in single drop mode.
Setting this bit will put the receive side into multi-drop mode. In multi-drop mode, the
IBM3206K0424 will support four configurations and four unique PHY ports. This bit
should not be set if the receive side is connected to the Internal SONET Framer. Con-
figuration 0 Receive Control Register will control the receive interface. If this bit is not
set, the IBM3206K0424 receive side is in single drop mode.
Description
IBM Processor for Network Resources
The PHY Interface (LINKC)
Page 405 of 676
IBM3206K0424