ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 103

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
1.7: PCINT Base Addresses 3-6 (Memory)
This register specifies the base address of where in PCI memory space the IBM3206K0424 memory will be
mapped. When written with ’1’s and read back, the least significant bits read back as ’0’ will indicate the
amount of memory space required for this device to operate. For example, when a value of ’FFFFFFFF’ is
written, a value read of ’FFFFFF00’ indicates that 256 bytes of address space this required. See bit defini-
tions.
The mapping for the base address of registers into IBM3206K0424 memory is one-to-one, assuming a mem-
ory windowing option is not set in the PCINT Base Addr Control Register for that base address register
(BAR). Multiple BARs are only used to use a given system memory map more efficiently. As required by the
BAR, the addresses are size-aligned. For example, that means a 16MB size could be represented with one
BAR as one 16MB size aligned on a 16MB boundary. However, four-4MB BARs could represent the same
16MB size but be aligned on any 4MB boundary. The value in any of the BARs does not map directly to any
particular IBM3206K0424 memory structure, such as Control Memory. The addresses are mapped using the
Virtual, Packet, and Control base address registers in VIMEN.
Length
Type
Address
Power on Reset value
(Big Endian)
Power on Reset value
(Little Endian)
Restrictions
When in 64-bit Addressing Mode (that is, bit 64 of PCINT 64-bit Control Register is set to ’1’):
pnr25.chapt04.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Bit(s)
31-0
PCI Spec
31-0
Upper part of Base Address
32 bits
Read/Write
Reg 3
Reg 4
Reg 5
Reg 6
X’00000008’
X’08000000’
Can be written or read during configuration cycle, memory cycle when enabled (see
PCINT Base Address Control Register on page 111), or an I/O cycle. This register
is documented as big endian, but how data is presented on the PCI bus depends
on how the controls are set in the PCINT Endian Control Register.
If one of these registers is not enabled (see PCINT Base Address Control Regis-
ter), then a read of that register will return all ’0’s. The power on value stated below
assumes that the register is enabled. Normally, configuration code will just read
these registers to find out what is there. To enable more that the default of registers
3 and 4, the use of Crisco code could be used. See Entity 15: on page 428 for
details.
Name
XXXX 0018
XXXX 001C
XXXX 0020
XXXX 0024
Base Address
This register is used to hold the upper 32 bits of address during a 64 bit
addressing dual cycle access.
The IOP Bus Specific Interface Controller (PCINT)
IBM Processor for Network Resources
Description
8
7
6
5
4
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IBM3206K0424
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