ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 430

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for
Register Initialization from EPROM Data
Page 430 of 676
Bit(s)
3-2
5
4
1
0
Do PHY Reset
Enable
PB0PHY2 Control
External EPROM Type
Reduce Serial EPROM clock
Name
Force a PHY logic reset. Before any software reset, turn this bit on and off for the PHY
specified amount of time. If the IBM ATM-TC (25 Mbps ENDEC) is used, this bit will
power-up to an active reset (since the input to the ENDEC is positive reset). This bit
must then be turned off for normal operation.
Enable the front end. When this bit is ’0’, no data will be transmitted to or received from
the PHYs or the IBM3206K0424. See bit 8 for more information on control of this bit.
Encoded control for the PB0PHY2 output pin. The enabled of PIBSELO overrides
these bits and is controlled by PCINT Cascade Control Register.
X’0’
X’1’
X’2’
X’3’
This bit will set at reset time as to what type of EPROM is detected. When set, a serial
EPROM has been detected. When a ’0’, parallel EPROM is assumed (or none at all).
This will also indicate from what type of device a PCI ROM access will retrieve VPD
data.
When set to ’1’, this bit is used for speeding up sim time for the serial EPROM. It will
change the time period for the serial EPROM clock from 10 µ s to 85 ns.
Enable PB0PHY2 pin
Enable PBDATAP pin and its detection of valid parity.
Enable MPMDSEL pin
Reserved
Description
pnr25.chapt05.01
August 14, 2000
Preliminary