ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 268

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Buffer Pool Management (POOLS)
Page 268 of 676
Bit(s)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Lock POOLs on Error
Packet High Priority on Get or
Free FIFOs Full
Packet High Priority Always
Control High Priority Always
Packet High Priority with Request
Timer
Control High Priority with Request
Timer
Fast Free Mode
Initialization Mode
Virtual Memory Mode
Limit Event Generation
Enable Event Interface
Enable Out of Range Index
Checking
Force All Queue Transactions to
Memory
Diagnostic Mode
Function
When set, this bit in conjunction with the lock mask will hold pools state machines in
an idle state until cleared.
When set, this bit causes pools to turn on its high priority request to Packet Memory
when either the free or get FIFO is full.
When set, this bit causes pools to always use its high priority request to Packet Mem-
ory.
When set, this bit causes pools to always use its high priority request to Control Mem-
ory.
When set, this bit causes pools to time the wait for Packet Memory service and when
the timer expires move to high priority.
When set, this bit causes pools to time the wait for Control Memory service and when
the timer expires move to high priority.
When this bit is set, Fast Free Mode is enabled. When pools is in Fast Free Mode it
does not write out the buffer map with the modified control information that indicates
that the map is unused. When in this mode unused buffer free error checking is dis-
abled.
When the value of the bit is ’0’, initialization mode is set. When the value is ’1’, opera-
tional mode is set. During initialization mode indexes are in the upper 16 bits of the
data word. It is assumed that when initialization mode is on other normal operations
are not active such as transmit or receive. During operational mode packet addresses
assumed to be on the data bus.
When set to ’0’, Virtual Memory mode is enabled. When set to ’1’, real memory mode
is enabled.
When set, this bit causes pools to limit the issuance of events to RXQUE when a
GTD threshold, Total Threshold or POOL Threshold is reached. It will issue the first
event and disable the related event enable bit. Software must then reset the bit if it
wishes to see another such event. However, it is possible that events may be lost
when this bit is set on.
When set, this bit causes pools to issue resource events to RXQUE when a GTD
threshold, Total Threshold or POOL Threshold is reached.
When set, this bit causes pools to check the indexes that are streaming by to be
checked against a maximum value for that size index. If the normal initialization
sequence is used, these maximum values will auto set.
When set, this bit disables the internal tail to head transfer path within the queue. All
indexes will proceed into memory before being brought to the head of the queue. This
effectively preserves the operational history in memory. However, some caution is
warranted since four full entries are required for a write to memory. This could cause
indexes to get "stuck" at the back of the queue. When this residue occurs, a zero
pointer is returned even though the operation might have otherwise returned a valid
pointer.
When set, pools is in diagnostic mode. When cleared, pools is in normal mode. When
in diagnostic mode, state machines are held in idle. If they are already active, when
they next go to idle they will hold there.
Description
pnr25.chapt04.01
August 14, 2000
Preliminary