ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 601

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
OFP_Rx GPP Handler Address Mapping
pnr25.chapt06.01
August 14, 2000
Register Name
1. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both
2. Address range 100-17F located in 128x8. GRA Address range 180-1BF located in 64x8 GRA.
3. The 64-byte J1 path trace processing uses the 16 byte addresses of 16 byte J1 path trace to map a full 64 byte space.
M_CntrIRQ1
M_CntrIRQ2
M_CntrIRQ3
ND_EVCNT
M_MainIRQ
CntrIRQ1
CntrIRQ2
CntrIRQ3
SOH-A11
SOH-A12
SOH-A13
SOH-A21
SOH-A22
SOH-A23
MainIRQ
M_IRQ6
M_IRQ7
M_IRQ8
SOH-J0
RESET
CONF1
CONF2
CONF3
CONF4
CONF7
CONF8
CONF9
STAT1
STAT2
STAT3
STAT4
yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the
counter after read operation.
IRQ6
IRQ7
IRQ8
New data event counter, no threshold
Default RESET register
Status register #1 (Mode)
Status register #2 (AU pointer)
Status register #3 (SOH)
Status register #4 (POH)
MAIN INTerrupt register
INTerrupt MASK register for MainIRQ
COUNTER INTerrupt register
INTerrupt MASK register for CntrIRQ1
COUNTER INTerrupt register
INTerrupt MASK register for CntrIRQ2
COUNTER INTerrupt register
INTerrupt MASK register for CntrIRQ3
USER INTerrupt register
INTerrupt MASK register for IRQ6
USER INTerrupt register
INTerrupt MASK register for IRQ7
USER INTerrupt register
INTerrupt MASK register for IRQ8
Configuration register #1 (general)
Configuration register #2 (SOH processing)
Configuration register #3 (POH processing)
Configuration register #4 (APS processing)
Configuration register #7 (miscellaneous)
Configuration register #8 (FSCR)
Configuration register #9 (SL)
First A1
Second1 A1
Third A1
First A2
Second A2
Third A2
J0
Reserved for national use and not included in frame scrambling
(C1)
Description
Base Address = x’800’ (Page 2 of 4)
1
Overhead Frame Processor Architecture: Receive Direction
Address Offset
IBM Processor for Network Resources
X’2C/2D’
X’107-8’
X’100’
X’101’
X’102’
X’103’
X’104’
X’105’
X’106’
X’3D’
X’3A’
X’3B’
X’3C’
X’3E’
X’3F’
X’4A’
X’4B’
X’4E’
X’4F’
X’30’
X’33’
X’34’
X’35’
X’36’
X’38’
X’39’
X’40’
X’41’
X’42’
X’43’
X’44’
X’45’
X’48’
X’49’
X’50’
1
Type Width
N 8
R 2
S 3
S 6
S 6
S 4
X 7
X 8
X 8
X 5
X 4
X 8
X 8
C 8
C 6
C 4
C 8
C 8
C 8
C 8
I 7
I 8
I 8
I 5
I 4
I 8
I 8
8
8
8
8
8
8
8
8
Page 601 of 676
IBM3206K0424
Initial Value
’00000000’
’00000000’
’00000000’
’00000000’
’00000000’
’00111111’
’00000000’
’00100000’
’11111110’
’00010011’
’0000000’
’00000’
’0000’
’0000’
’0000’
’01’