ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 259

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
9.9: POOLS Pointer Queues DRAM Upper Bound Register
The POOLS Pointer Queues DRAM Upper Bound Register indicates the max queue length in DRAM of the
queue data structure. When the queue reaches this address, it wraps back to the address specified by the
lower bound register. This implements the queue in a circular buffer. This upper bound is to be provided as an
encoded field. The encoded field represents the number of eight-byte addresses that can be contained by the
queue.
These four bits represent the encoded maximum queue length in DRAM which, when matched, trigger the
queue to wrap back to the address contained in the DRAM Lower Bound Address Register.
Length
Type
Address
Power on Value
Restrictions
pnr25.chapt04.01
August 14, 2000
4 bits
Read/Write
Buffer Size 0
Buffer Size 1
Buffer Size 2
Buffer Size 3
Virtual Packets/
Buffer Size 4
Buffer Size 0
Buffer Size 1
Buffer Size 2
Buffer Size 3
Virtual Packets/
Buffer Size 4
During normal operations, this register is to be used as a read only register. This regis-
ter should be setup at initialization time. The size of the DRAM queue storage which is
formed with the lower and upper bounds is constrained in its size. It can be written
when the diagnostic mode bit is set, otherwise the write is ignored. Note that if the max-
imum queue length exceeds the space available in the circular buffer, data corruption
will occur when the actual queue length exceeds the maximum queue space available.
XXXX 3050
XXXX 3054
XXXX 3058
XXXX 305C
XXXX 3060
X’B’
X’A’
X’9’
X’9’
X’B’
IBM Processor for Network Resources
Buffer Pool Management (POOLS)
Page 259 of 676
IBM3206K0424