ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 120

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
The IOP Bus Specific Interface Controller (PCINT)
Page 120 of 676
21-20
17-16
15-12
Bit(s)
11-8
7-4
3-0
19
18
Data Transfer Width
Control - Counter 1
Data Direction - Counter 2
Data Direction - Counter 1
Counter Modes
Master/Slave Types - Counter 2
Cycles Types - Counter 2
Master/Slave Types - Counter 1
Cycles Types - Counter 1
Function
These bits will determine which kind of cycle to count based on the
transfer size for counter 1.
X’0’: All transfers
X’1’: 32 bit transfers only
X’2’: 64 bit transfers only
X’3’: Enable Data Direction (bits 18 or 19)
These bits will determine which kind of cycle to count based on the data direction - in
or out of the IBM3206K0424 for counter 2.
These bits will determine which kind of cycle to count based on the data direction - in
or out of the IBM3206K0424 for counter 1.
X’0’: Data In
X’1’: Data Out
These bits will determine which kind of mode both counters will operate in.
X’0’ Stop on overflow
X’1’ Interrupt on wrap
X’2’ Event on wrap
X’3’ Inject active errors on overflow
These bits determine which kind of PCI cycle owners to be counted for counter 2. The
definitions are the same as bits 7-4.
These bits determine what kind of PCI events are to be counted for counter 2. The
definitions are the same as bits 3-0.
These bits determine which kind of PCI cycle owners to be counted for counter 1.
X’0’ All Devices on the PCI bus
X’1’ All Devices but IBM3206K0424
X’2’ IBM3206K0424 only (master or slave)
X’3’ IBM3206K0424 master
X’4’ IBM3206K0424 slave (all types)
X’5’ IBM3206K0424 slave register accesses
X’6’ IBM3206K0424 slave memory accesses
These bits will determine what kind of PCI events are to be counted for counter 1.
X’0’ Off
X’1’ All PCI clock cycles
X’2’ Active PCI bus cycles (frame + irdy + trdy)
X’3’ PCI Data Xfer Opportunities ((irdy + trdy) & devsel)
X’4’ PCI Data Xfers (irdy & trdy)
X’5’ PCI Retries (irdy & no trdy & devsel & stop)
X’6’ PCI Address Phase (frame & not frame delayed)
X’7’ PCI Disconnects (irdy & trdy & devsel & stop)
Description
pnr25.chapt04.01
August 14, 2000
Preliminary