ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 256

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
9.6: POOLS Pointer Queues DRAM Head Pointer Offset Address Register
The POOLS Pointer Queues DRAM Head Pointer Offset Address Register indicates the address in DRAM
where the head of the queue starts. This address, however, is only relative to the DRAM portion of the queue.
Unless the head of the queue portion of the cache is locked out and needs two frames, the actual head of the
queue is in the cache.
These 19 bits on write represent the offset to the address in DRAM of the head of the queue relative to the
DRAM base address. On a read, the address in DRAM of the pointer is returned. This pointer is adjusted
every time a cache frame boundary is crossed and a cache update cycle is completed to write through the
additional queue elements. Because each memory reference contains four indices, this allows for a possible
128K index locations in the queue.
Length
Type
Address
Power on Value
Restrictions
Buffer Pool Management (POOLS)
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32 bits Read/19 bits Write
Read/Write
Buffer Size 0
Buffer Size 1
Buffer Size 2
Buffer Size 3
Virtual Packets/
Buffer Size 4
Buffer Size 0
Buffer Size 1
Buffer Size 2
Buffer Size 3
Virtual Packets/
Buffer Size 4
During normal operations this register is to be used as a read only register. This regis-
ter defaults to zero at initialization. It is assumed that the queues start on a maximum
size queue boundary. These registers should be set up at initialization time. This regis-
ter is cleared when the POOLS Pointer Queues DRAM Lower Bound Address Register
is written to.
XXXX 3014
XXXX 3018
XXXX 301C
XXXX 3020
XXXX 3024
X’00 01 C0 00’
X’00 02 00 00’
X’00 02 40 00’
X’00 02 60 00’
X’00 02 70 00’
pnr25.chapt04.01
August 14, 2000
Preliminary