ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 428

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Entity 15: Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register
Initialization from EPROM Data
This entity controls the signals of the NPBUS. The PHY registers are accessible to the processor by way of
the address space of the IBM3206K0424. In addition, the operation of the front end is affected by the NPBUS
Status Register.
This entity also contains the CRISCO processor which can initialize chip registers at boot time by reading a
data stream from EPROM which specifies the address of registers and data values to which the registers are
to be initialized. In general, the data stream consists of a series of single-byte instruction operation codes,
followed by an address and data values.
15.1: NPBUS Control Register
This register is used to report PHY level hardware errors and interrupts. See Note on Set/Clear Type Regis-
ters on page 93 for more details on addressing.
Length
Type
Address
Power On Value
Restrictions
Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for
Register Initialization from EPROM Data
Page 428 of 676
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Bit(s)
28
27
Enable PHY Addr/Data multiplex-
ing
Status LED 4 Toggle
Name
29 bits
Clear/Set
XXXX 2000 and 004
X’0002010’
None
This bit set to ’1’ will enable the ALE1, ALE2, and ALE3 control lines for PHY and Par-
allel EPROM accesses so that additional address bytes can be latched for up to
24Meg of addressing. Since there is an access speed penalty for this, the default is a
’0’ for this function.
When this bit is set, the state of bit 19 of this register will be toggled by repeatedly set-
ting bit 19.
14
13 12 11 10 9
8
Description
7
6
5
4
3
2
1
pnr25.chapt05.01
August 14, 2000
0
Preliminary