ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 113

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
1.15: PCINT Window Offsets for Base Addresses 3-6
These registers specify the amount of memory space required for this device to operate. See bit definitions.
Length
Type
Address
Power on Value
Restrictions
pnr25.chapt04.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31-14
Bit(s)
13-0
Windowing Offset Range.
Reserved.
Function
Windowing Offset Range
32 bits
Read/Write
Reg 3
Reg 4
Reg 5
Reg 6
X’00000000’
Can be written or read during configuration cycle, memory cycle when enabled (see
PCINT Base Address Control Register on page 111), or an I/O cycle. This register
is documented as big endian, but how data is presented on the PCI bus depends
on how the controls are set in the PCINT Endian Control Register.
This register is used to hold the address offset, which is added to the PCI address (when
windowing is enabled) to form the internal memory address. Bits 15 and 14 may or may not
be used, depending on how bits are set in the PCINT Base Address Control Register.
When bit 20 of PCINT Count Timeout Register is set, Window Offset register three can be
updated with the address returned from a good get buffer from POOLS. This will save a
write from code to this register.
When bit 20 of PCINT Count Timeout Register is set, Window Offset register four can be
updated with the address returned from a dequeue from the receive queue. This will save a
write from code to this register.
Reserved
XXXX 0060
XXXX 0064
XXXX 0068
XXXX 006C
Description
The IOP Bus Specific Interface Controller (PCINT)
IBM Processor for Network Resources
8
Reserved
7
6
5
4
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IBM3206K0424
3
2
1
0