ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 59

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Clock, Configuration, and LSSD Pin Descriptions
pnr25.chapt02.01
August 14, 2000
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PLLTUNE(1:0)
MPLLRESET
JTCOMPLY
JTAGTDO
PDBLCLK
PPLLOUT
LEAKTST
Pin Name
BISTnDI1
PINTCLK
IBDINH1
IBDINH2
IBDRINH
RXD
DSR
DTR
CTS
TXD
RTS
Input or Output
Input or Output
Input or Output
Input or Output
Input or Output
Input/Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Test Data Output is used to serially shift test data and test instructions out of the
device during TAP operation. (LSSD test function - PRSRAMABDONE and
PLLLOCK output)
This is the external test point to measure the jitter effects of the phase-lock loop
circuit. PINTCLK does not serve any LSSD or MFG test function. It does not
need to be on a TEST/NOSCAN location.
This is the external test point that is double the frequency of the PINTCLK. It is
used to clock ENSTATE state signals at this frequency. PDBLCLK does not
serve any LSSD or MFG test function. It does not need to be on a TEST/NOS-
CAN location.
This is an observation output only. This makes the output of the PLL observ-
able. This is also the DTR signal when the SELRS232 is active.
Drives the DI input during BIST.
RS232 DTR for the core debugger. (LSSD test function - TCLKA-AC)
RS232 CTS for the core debugger. (LSSD test function - LPRA bypass-TI)
RS232 TXD for the core debugger. (LSSD test function - CLKDIVTCLKB-BC)
RS232 RXD for the core debugger. (LSSD test function - BSCANTCLKB-BC)
RS232 RTS for the core debugger. (LSSD test function - BSCANTCLKC-SC)
RS232 DSR for the core debugger. (LSSD test function - pll testout)
This is the Boundary Scan input for BSINH1.
This is the Boundary Scan input for BSINH2(*).
This is the Boundary Scan input for rinh.
This is the STI driver/receiver leak test input.
These inputs help tune the PLL operation. (LSSD test function -
SCANOUT(15,14))
This input is active low and resets the PLL at power up to avoid VCO runaway.
This requires a reset circuit that delays a low-to-high level after power-on-reset
by 150 µ s. (LSSD test function - this pin functions as the TESTCT [Test Clock
Tree] input. When not asserted, this chip runs as specified. When asserted, the
clock tree uses this input to control the clokc tree outputs - TI)
This input is high for JTAG compliance and low for RISCWatch/BIST-friendly
use. When this pin is high, JTAG boundary scan operations may be used to test
chip I/O operation and card wiring without supplying clocks to the rest of the
chip. Also, when the TAP controller enters the TEST LOGIC RESET state, the
JTAG instruction is IDCODE. When this pin is low, the JTAG boundary scan
logic works only if the other chip clocks are running in a normal functional man-
ner. When the TAP controller enters the TEST LOGIC RESET state, the JTAG
instruction is BYPASS in order to make this more compatible with RISCWatch.
(LSSD test function - SRAM BIST result output)
(Continued)
Pin Description
IBM Processor for Network Resources
ATM PHY Bus Interface
IBM3206K0424
Page 59 of 676